Infineon/CYPRESS CY9AF314NAPMC-GNE2

The CY9A310A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded control applications. The CY9A310A Series are based on the Arm Cortex-M3 Processor and on-chip Flash memory and SRAM, and peripheral functions, including Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I²C, LIN).

• Processor version: r2p1
• Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1,2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
• EndPoint 3,4 and 5 can be selected Bulk-transfer, Interrupt-transfer
• EndPoint1 - 5 is comprised Double Buffer
• Endpoint 0, 2 to 5: 64bytes
• Endpoint 1: 256bytes
• Up to 512 Kbyte
• Read cycle: 0 wait-cycle
• Security function for code protection
• This Series contain a total of up to 32 Kbyte on-chip SRAM. On-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
• SRAM0: Up to 16 Kbytes
• SRAM1: Up to 16 Kbytes
• USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
• Up to 40 MHz Frequency Operation
• USB2.0 Full-Speed supported
• USB2.0 Full/Low speed supported
• Bulk-transfer, interrupt-transfer and Isochronous-transfer support
• USB Device connected/dis-connected automatically detect
• IN/OUT token handshake packet automatically
• Max 256 - byte packet-length supported
• Wake-up function supported
• 4 channels with 16 steps × 9bit FIFO (ch.4 - ch.7), 4 channels without FIFO (ch.0 - ch.3)
• Operation mode is selectable from the followings for each channel: UART, CSIO, LIN, I²C
• Full duplex double buffer
• Selection with or without parity supported
• Built-in dedicated baud rate generator
• External clock available as a serial clock
• Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)
• Various error detection functions available (parity errors, framing errors, and overrun errors)
• Full-duplex double buffer
• Built-in dedicated baud rate generator
• Overrun error detection function available
• LIN protocol Rev.2.1 supported
• Full-duplex double buffer
• Master/Slave mode supported
• LIN break field generation (can be changed 13 - 16bit length)
• The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
• Transfer can be started by software or request from the built-in peripherals
• Transfer address area: 32 bit (4 Gbytes)
• Transfer mode: Block transfer/Burst transfer/Demand transfer
• Transfer data type: byte/half-word/word
• Transfer block count: 1 to 16
• Number of transfers: 1 to 65536
• Successive Approximation type
• Built-in 3units
• Conversion time: 1.0 μs@5 V
• Standard-mode (Max 100kbps) / Fast-mode (Max 400kbps) supported
• Supports SRAM, NOR Flash device
• Up to 8 chip selects
• 8-/16-bit Data width
• Up to 25-bit Address bit
• Maximum area size: Up to 256 Mbytes
• Operation mode is selectable from the followings for each channel: 16-bit PWM timer, 16-bit PPG timer, 16-/32-bit reload timer, 16-/32-bit PWC timer
• The Multi-function timer is composed of the following blocks: 16-bit free-run timer × 3 ch/unit, Input capture × 4 ch/unit, Output compare × 6 ch/unit, A/D activation compare × 3 ch/unit, Waveform generator × 3 ch/unit, 16-bit PPG timer × 3 ch/unit
• The following function can be used to achieve the motor control: PWM signal output function, DC chopper waveform output function, Dead time function, Input capture function, A/D converter activate function, DTIF (Motor emergency stop) interrupt function
• The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.
• Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
• The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
• 16-bit position counter
• 16-bit revolution counter
• Two 16-bit compare registers
• The Watch counter is used for wake up from Low-Power Consumption mode.
• A watchdog timer can generate interrupts or a reset when a time-out value is reached.
• The Dual Timer consists of two programmable 32-/16-bit down counters.
• Operation mode is selectable from the followings for each timer channel.
• This series consists of two different watchdogs, a "Hardware" watchdog and a, "Software" watchdog.
• Free-running