Infineon/CYPRESS MB91F592BHPMC-GSK5E1

This series is 32-bit microcontroller designed for automotive and industrial control applications. It contains the FR81S CPU that is compatible with the FR family. The FR81S has a high level performance among the FR family by enhancing CPU instruction pipeline and load store processing, and improving internal bus transfer. It is best suited for application control for automotive.

• FR81S CPU Core:
  • 32-bit RISC, load/store architecture, pipeline 5-stage structure
  • Maximum operating frequency: 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied (PLL clock multiplication system))
  • General-purpose register: 32 bits × 16 sets
  • 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
  • Instructions appropriate to embedded applications: Memory-to-memory transfer instruction, Bit processing instruction, Barrel shift instruction etc.
  • High-level language support instructions: Function entry/exit instructions, Register content multi-load and store instructions, Bit search instructions, Logical 1 detection, 0 detection, and change-point detection
  • Branch instructions with delay slot: Reduced overhead during branch process
  • Register interlock function: Easy assembler writing
  • The support at the built-in / instruction level of the multiplier: Signed 32-bit multiplication: 5 cycles, Signed 16-bit multiplication: 3 cycles
  • Interrupt (PC/PS saving): 6 cycles (16 priority levels)
  • The Harvard architecture allows simultaneous execution of program and data access.
  • Instruction compatibility with the FR Family
  • Built-in memory protection function (MPU): Eight protection areas can be specified commonly for instructions and the data, Control access privilege in both privilege mode and user mode.
  • Built-in FPU (floating point arithmetic) IEEE754 compliant, Floating-point register 32-bit × 16 sets
• Peripheral Functions:
  • Clock generation (equipped with SSCG function): Main oscillation (4 MHz), Sub oscillation (32 kHz) or none sub oscillation, PLL multiplication rate: 1 to 32 times
  • Built-in Program flash memory capacity 2048 + 64 KB (series maximum)
  • Built-in Data flash memory capacity(WorkFlash) 64KB
  • Built-in RAM capacity: Main RAM 192 KB (Series maximum), Sub RAM (on AHB) 64 KB (Series maximum), Backup RAM 8 KB
  • General-purpose ports (5V Pin): 63 (dual clock products: 61), Included I²C pseudo open drain support ports: 4
  • General-purpose ports (3V Pin): 93, Included 48 combined external bus interface (For GDC external memory I/F)
  • External bus interface: GDC external memory for I/F use, 25-bit address, 16-bit data, Power supply voltage fixed to 3.3 V
  • DMA Controller: Up to 16 channels can be started simultaneously, 2 transfer factors (Internal peripheral request and software)
  • A/D converter (successive approximation type): 8/10 -bit resolution: 32 channels, Conversion time: 3 μs
  • External interrupt input: 16 channels, Level ("H" / "L"), or edge detection (rising or falling) enabled
  • LIN-UART: 6 channels, ch.2 to ch.7, UART, synchronous mode, LIN-UART mode is selectable, LIN protocol Revision 2.1 is supported, SPI (Serial Peripheral Interface) supported (synchronous mode), Full-duplex double buffering system, LIN synch break detection (linked to the input capture), Built-in dedicated baud rate generator, DMA transfer support
  • Multi-function serial communication (built-in transmission/reception FIFO memory): 2 channels for CY91F591/2/4/6/7/9, 6 channels for CY91F59A/B
    • UART (Asynchronous serial interface): Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory, Parity or no parity is selectable, Built-in dedicated baud rate generator, An external clock can be used as the transfer clock, Parity, frame, and overrun error detect functions provided, DMA transfer support
    • CSIO (Synchronous serial interface): Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory, SPI supported; master and slave systems supported; 5 to 9-bit data length can be set, Built-in dedicated baud rate generator (Master operation), An external clock can be entered. (Slave operation), Overrun error detect function is provided, DMA transfer support
    • LIN-UART (Asynchronous Serial Interface for LIN): Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory, LIN protocol Revision 2.1 supported, Master and slave systems supported, Framing error and overrun error detection, LIN synch break generation and detection; LIN synch delimiter generation, Built-in dedicated baud rate generator, An external clock can be adjusted by the reload counter, DMA transfer support
    • I²C: ch.0 and ch.1 only supported, Full-duplex double buffering system, 16-byte transmission FIFO memory, 16-byte reception FIFO memory, Standard mode (Max. 100kbps) / high-speed mode (Max. 400kbps) supported, DMA transfer supported

• automotive
• industrial control