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MXIC MX25U25645GXDI00

Produttore
MXIC
Cod. Prod.
MX25U25645GXDI00
Cod. LCSC
C2802880
Imballo
CSPBGA-24(6x8)
Numero Cliente
Attr. chiave
256Mbit 1.65V~2V 166MHz SPI CSPBGA-24(6x8) Memory RoHS
Scheda TecnicaMXIC MX25U25645GXDI00
Parti alternative10
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 6.5877$ 6.59
10+$ 6.4953$ 64.95
30+$ 6.4331$ 192.99
100+$ 6.3726$ 637.26
Package Standard5/Full Tray
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Memory/Memory
ProduttoreMXIC
ImballoCSPBGA-24(6x8)
Operating Temperature-40℃~+85℃
FeaturesWrite enable latch;Power-on reset;Hardware write protection;Software write protection;Absolute write protection
Memory Size256Mbit
Voltage - Supply1.65V~2V
Program / Erase Cycles100,000 cycles
Clock Frequency166MHz
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)-
Write Cycle Time(tWC)-
Page Programming Time (Tpp)750us
Standby Supply Current-
InterfaceSPI
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Caratteristiche

Traduzione AI
  • Multi I/O Support - Single I/O, Dual I/O and Quad I/O
  • Support DTR (Double Transfer Rate) Mode
  • 8/16/32/64 byte Wrap-Around Read Mode
  • Supports Serial Peripheral Interface -- Mode 0 and Mode 3
  • Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations
  • 256Mb: 268,435,456 x 1 bit structure or 134,217,728 x2 bits (two I/O mode) structure or 67,108,864x4 bits (four I/O mode) structure
  • Protocol Support - Single I/O, Dual I/O and Quad I/O
  • Latch-up protected to 100mA from -1V to Vcc +1V
  • Fast read for SPI mode - Support fast clock frequency up to 166MHz - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions - Support DTR (Double Transfer Rate) Mode - Configurable dummy cycle number for fast read operation Support Performance Enhance Mode - XIP (execute-in-place) Quad Peripheral Interface (QPI) available Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
  • Programming : - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance Typical 100,000 erase/program cycles
  • 20 years data retention
  • Input Data Format: 1-byte Command code
  • Advanced Security Features: Block lock protection. The BP0 - BP3 and T/B status bits define the size of the area to be protected against program and erase instructions
  • Advanced sector protection function
  • Additional 8K bit security OTP: Features unique identifier, Factory locked identifiable, and customer lockable
  • Command Reset
  • Program/Erase Suspend and Resume operation
  • Electronic Identification - JEDEC 1 - byte manufacturer ID and 2 - byte device ID - RES command for 1 - byte Device ID - REMS command for 1 - byte manufacturer ID and 1 - byte device ID
  • Support Serial Flash Discoverable Parameters (SFDP) mode
  • SCLK Input: Serial clock input
  • SI/SIO0: Serial Data Input or Serial Data Input/Output for 2x1/O read mode and 4x1/0 read mode
  • SO/SIO1: Serial Data Output or Serial Data Input/Output for 2x1/0 read mode and 4x1/0 read mode

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