MICROCHIP CRT9007DECCD

The CRT9007 VPAC is a next generation video processor/controller - an MOS LSI integrated circuit which supports either sequential or row - table driven memory addressing modes. As indicated by the features above, the VPAC provides the user with a wide range of programmable features permitting low cost implementation of high performance CRT systems. Its 14 address lines can directly address up to 16K of video memory. This is equivalent to eight pages of an 80 character by 24 line CRT display. Smooth or jump scroll operations may be performed anywhere within the addressable memory. In addition, status rows can be defined anywhere on the screen.

In the sequential video addressing mode, a Table Start Register points to the address of the first character of the first data row on the screen. It can be easily changed to produce a scrolling effect on the screen. By using this register in conjunction with two auxiliary address registers and two sequential break registers, a screen roll can be produced with a stable status row held at either the first or last data row position.

In the row - table driven video addressing mode, each row in the video display is designated by its own address. This provides the user with greater flexibility than sequential addressing since the rows of characters are linked by pointers instead of residing in sequential memory locations. Operations such as data row insertion, deletion, and replication are easily accomplished by manipulating pointers instead of entire lines. The row table itself can be stored in memory in a linked list or in a contiguous format. The VPAC works with a variety of memory contention schemes including operation with a Single Row Buffer such as the CRT9006, a Double Row Buffer such as the CRT9212, or no buffer at all, in which case character addresses are output during each displayable scan line.

User accessable internal registers provide such features as light pen, interrupt enabling, cursor addressing, and VPAC status. Ten of these registers are used for screen formatting with the ability to define over 200 characters per data row and up to 256 data rows per frame. These 10 registers contain the "vital screen parameters".

• Fully Programmable Display Format: Characters per Data Row (8 - 240), Data Rows per Frame (2 - 256), Raster Scans per Data Row (1 - 32)
• Programmable Monitor Sync Format: Raster Scans/Frame (4 - 2048), Front Porch —— Horizontal (Negative or Positive), Vertical Sync Width - Horizontal (1 - 128 Character Times), Vertical (2 - 256 Scan Lines), Back Porch — Horizontal, - Vertical
• Direct Outputs to CRT Monitor: Horizontal Sync, Vertical Sync, Composite Sync, Composite Blanking, Cursor Coincidence
• Binary Addressing of Video Memory
• Row - Table Driven or Sequential Video Addressing Modes
• Programmable Status Row Position and Address Registers
• Bidirectional Partial or Full Page Smooth Scroll
• Attribute Assemble Mode
• Double Height Data Row Mode
• Double Width Data Row Mode
• Programmable DMA Burst Mode
• Configurable with a Variety of Memory Contention Arrangements
• Light Pen Register
• Cursor Horizontal and Vertical Position Registers
• Maskable Processor Interrupt Line
• Internal Status Register
• Three - state Video Memory Address Bus
• Partial or Full Page Blank Capability
• Two Interlace Modes: Enhanced Video and Alternate Scan Line
• Ability to Delay Cursor and Blanking with respect to Active Video
• Programmable for Horizontal Split Screen Applications
• Graphics Compatible
• Ability to Externally Sync each Raster Line, each Field
• Single +5 Volt Power Supply
• TTL Compatible on All Inputs and Outputs
• VT - 100 Compatible
• RS - 170 Interlaced Composite Sync Available