Intel/Altera EP3C25F256C7

Cyclone III device family offers a unique combination of high functionality, low power and low cost. Based on TSMC low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than % watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

• Lowest power consumption with TSMC low-power process technology and Altera power-aware design flow
• Extended battery life for portable and handheld applications
• Reduced or eliminated cooling system costs
• Operation in thermally-challenged environments
• Hot-socketing operation support
• Configuration security using advanced encryption standard (AES) with 256-bit volatile key
• Routing architecture optimized for design separation flow with the Quartus II software
• Design separation flow achieves both physical and functional isolation between design partitions
• Ability to disable external JTAG port
• Error Detection (ED) Cycle Indicator to core
• Provides a pass or fail indicator at every ED cycle
• Provides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits
• Ability to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key
• Internal oscillator enables system monitor and health check capabilities
• High memory-to-logic and multiplier-to-logic ratio
• High I/O count, low-and mid-range density devices for user I/O constrained applications
• Adjustable I/O slew rates to improve signal integrity
• Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
• Supports the multi-value on-chip termination (OCT) calibration feature to eliminate variations over process, voltage, and temperature (PVT)
• Four phase-locked loops (PLLs) per device provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces
• Five outputs per PLL
• Cascadable to save I/Os, ease PCB routing, and reduce jitter
• Remote system upgrade without the aid of an external controller
• Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues
• Nios II embedded processor for Cyclone III device family, offering low cost and custom-fit embedded processing solutions
• Wide collection of pre-built and verified IP cores from Altera and Altera Megafunction Partners Program (AMPP) partners
• Supports high-speed external memory interfaces such as DDR, DDR2, SDR SDRAM, and QDRII SRAM
• Auto-calibrating PHY feature eases the timing closure process and eliminates variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
• Cyclone III device family supports vertical migration that allows you to migrate your device to other devices with the same dedicated pins, configuration pins, and power pins for a given package - across device densities