TI JM54AC373SSA-RH

The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OC (overline) is HIGH, the bus output is in the high impedance state. The ’AC/’ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dₙ inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE (overline)) input. When OE (overline) is LOW, the standard outputs are in the 2-state mode. When OE (overline) is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

• ICC and |oz reduced by 50%
• Eight latches in a single package
• TRI-STATE outputs for bus interfacing
• Outputs source/sink 24 mA
• ’ACT373 has TTL-compatible inputs
• Standard Microcircuit Drawing (SMD) — ’AC373: 5962-87555 — ’ACT373: 5962-87556