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ST STM32MP135FAE7

Produttore
ST
Cod. Prod.
STM32MP135FAE7
Cod. LCSC
C7501745
Imballo
LFBGA-289(14x14)
Numero Cliente
Attr. chiave
Arm Cortex - A7 up to 1 GHz, LCD - TFT, camera interface, 2xETH, 2xCAN FD, 2xADC, 24 timers, audio, crypto and adv.security
Scheda TecnicaST STM32MP135FAE7
Disponibile: 1
1 Pronta consegna
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.Importo totale
1+$ 11.1169$ 11.12
10+$ 10.7219$ 107.22
Package Standard1000/Full Reel
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Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microprocessors
ProduttoreST
ImballoLFBGA-289(14x14)
ADC (Bit)12bit
FeaturesPower-on reset (POR);Power-down reset (PDR);Undervoltage detection (BOR/LVD/LVR/LVI);Independent watchdog (IWDG);Calendar function;Storage encryption;True random number generator (TRNG);Hardware CRC;Built-in general-purpose timer;Built-in temperature sensor
CPU CoreARM Cortex-A7
CPU Maximum Speed650MHz
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Caratteristiche

Traduzione AI
  • Includes ST state-of-the-art patented technology
  • Core: 32-bit Arm Cortex-A7, L1 32-Kbyte I / 32-Kbyte D, 128-Kbyte unified level 2 cache, Arm NEON and Arm TrustZone
  • Memories: External DDR memory up to 1 Gbyte, up to LPDDR2/LPDDR3 - 1066 16-bit, up to DDR3/DDR3L - 1066 16-bit; 168 Kbytes of internal SRAM (128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain); Dual Quad-SPI memory interface; Flexible external memory controller with up to 16-bit data bus (parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC)
  • Security/safety: Secure boot, TrustZone peripherals, 12 x tamper pins including 5 x active tampers; Temperature, voltage, frequency and 32 kHz monitoring
  • Reset and power management: 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os); POR, PDR, PVD and BOR; On-chip LDOs (USB 1.8 V, 1.1 V); Backup regulator (~0.9 V); Internal temperature sensors; Low-power modes: Sleep, Stop, LPLV-Stop, LPLV-Stop2 and Standby; DDR retention in Standby mode; Controls for PMIC companion chip
  • Clock management: Internal oscillators (64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator); External oscillators (8 - 48 MHz HSE oscillator, 32.768 kHz LSE oscillator); 4 × PLLs with fractional mode
  • General-purpose input/outputs: Up to 135 secure I/O ports with interrupt capability; Up to 6 wakeup
  • Interconnect matrix: 2 bus matrices; 64-bit Arm AMBA AXI interconnect, up to 266 MHz; 32-bit Arm AMBA AHB interconnect, up to 209 MHz
  • 4 DMA controllers to unload the CPU: 56 physical channels in total; 1 x high-speed general-purpose master direct memory access controller (MDMA); 3 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management
  • Up to 30 communication peripherals: 5×I²C FM + 1 Mbit/s, SMBus/PMBus; 4×UART + 4×USART 12.5 Mbit/s, ISO7816 interface, LIN, IIDA, SPI slave; 5×SPI (50 Mbit/s, including 4 with full-duplex I²S audio class accuracy via internal audio PLL or external clock); 2×SAI (stereo audio: I²S PDM, SPDIF Tx), SPDIF Rx with 4 inputs; 2×SDMMC up to 8 bits (SD/e-MMCTM/SDIO); 2×CAN controllers supporting CAN FD protocol; 2×USB2.0 high-speed Host or 1×USB2.0 high-speed Host + 1×USB2.0 high-speed OTG simultaneously; 2×Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGMII; 8- to 16-bit camera interface, 3 Mpix @30 fps or 5Mpix @15 fps in color or monochrome with pixel clock @120 MHz (max freq)
  • 6 analog peripherals: 2×ADCs with 12-bit max. resolution up to 5 Msps; 1×temperature sensor; 1×digital filter for sigma-delta modulator (DFSDM) with 4 channels and 2 filters; Internal or external ADC reference VREF+
  • Graphics: LCD-TFT controller, up to 24-bit // RGB888; up to WXGA (1366 x 768) @60 fps or up to Full HD (1920 x 1080) @ 30 fps; pixel clock up to 90 MHz; two layers (incl. 1 secured) with programmable color LUT
  • Up to 24 timers and 2 watchdogs: 2×32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input; 2×16-bit advanced timers; 10×16-bit general-purpose timers (including 2 basic timers without PWM); 5×16-bit low-power timers; Secure RTC with sub-second accuracy and hardware calenocar; 4 Cortex-A7 system timers (secure, non-secure, virtual, hypervisor); 2×independent watchdogs
  • Hardware acceleration: AES 128, 192, 256 DES/TDES; AES 128, 256 with DPA protection; PKA ECC/RSA with DPA protection; AES 128 on-the-fly DRAM encryption and decryption; HASH (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-3), HMAC; 1 x true random number generator (6 triple oscillators); 1 x CRC calculation unit
  • Debug mode: Arm CoreSight trace and debug: SWD and JTAG interfaces usable as GPIOs; 4-Kbyte embedded trace buffer
  • 3072-bit fuses including 96-bit unique ID, up to 1280 bits available for user and 256-bit HUK to protect AES 256 keys
  • All packages are ECOPACK2 compliant