TI CD4044BPWR
| 제조업체 | |
| 제조사 품번 | CD4044BPWR |
| LCSC 번호 | C74801 |
| 포장 | TSSOP-16 |
| 고객 번호 | |
| 주요 제원 | CMOS Quad 3-State R/S Latches |
| 데이터시트 | TI CD4044BPWR |
| RoHS 준수 | 2개 문서 이용 가능 |
| 대체 부품 | 1 |
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | TI | |
| 포장 | TSSOP-16 | |
| Quiescent Current | 1uA | |
| Series | 4000B | |
| Logic Type | SR Latch | |
| Voltage - Supply | 3V~18V | |
| Current - Output Low(IOL) | 6.8mA | |
| Operating Temperature | -55℃~+125℃ | |
| Output Type | Tri-State | |
| Setup Time | - | |
| Number of Gates | 4 | |
| Current - Output High(IOH) | 6.8mA | |
| Hold Time | - | |
| Propagation Delay | 50ns |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | TI | |
| 포장 | TSSOP-16 | |
| Quiescent Current | 1uA | |
| Series | 4000B | |
| Logic Type | SR Latch | |
| Voltage - Supply | 3V~18V | |
| Current - Output Low(IOL) | 6.8mA |
| 타입 | 설명 | |
|---|---|---|
| Operating Temperature | -55℃~+125℃ | |
| Output Type | Tri-State | |
| Setup Time | - | |
| Number of Gates | 4 | |
| Current - Output High(IOH) | 6.8mA | |
| Hold Time | - | |
| Propagation Delay | 50ns |
개요
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The ppen circuit feature allows common busing of the outputs.
주요 특징
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of μA at 78V over full package temperature range; 100 nA at 18 V and 25℃
- Noise margin (over full package temperature range): 1 V at VDD = 5V; 2V at VDD = 10V; 2.5V at VDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, *Standard Specifications for Description of B' Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
응용 분야
- Holding register in multi-register system
- Strobed register
- General digital logic
| 수량 | 단가 | 총액 |
|---|---|---|
| 1+ | $ 0.5048 | $ 0.50 |
| 10+ | $ 0.4032 | $ 4.03 |
| 30+ | $ 0.3606 | $ 10.82 |
| 100+ | $ 0.3049 | $ 30.49 |
| 500+ | $ 0.2803 | $ 140.15 |
| 1,000+ | $ 0.2573 | $ 257.30 |
표준 패키지2000/Full Reel | ||
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | TI | |
| 포장 | TSSOP-16 | |
| Quiescent Current | 1uA | |
| Series | 4000B | |
| Logic Type | SR Latch | |
| Voltage - Supply | 3V~18V | |
| Current - Output Low(IOL) | 6.8mA | |
| Operating Temperature | -55℃~+125℃ | |
| Output Type | Tri-State | |
| Setup Time | - | |
| Number of Gates | 4 | |
| Current - Output High(IOH) | 6.8mA | |
| Hold Time | - | |
| Propagation Delay | 50ns |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | TI | |
| 포장 | TSSOP-16 | |
| Quiescent Current | 1uA | |
| Series | 4000B | |
| Logic Type | SR Latch | |
| Voltage - Supply | 3V~18V | |
| Current - Output Low(IOL) | 6.8mA |
| 타입 | 설명 | |
|---|---|---|
| Operating Temperature | -55℃~+125℃ | |
| Output Type | Tri-State | |
| Setup Time | - | |
| Number of Gates | 4 | |
| Current - Output High(IOH) | 6.8mA | |
| Hold Time | - | |
| Propagation Delay | 50ns |
개요
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The ppen circuit feature allows common busing of the outputs.
주요 특징
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of μA at 78V over full package temperature range; 100 nA at 18 V and 25℃
- Noise margin (over full package temperature range): 1 V at VDD = 5V; 2V at VDD = 10V; 2.5V at VDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, *Standard Specifications for Description of B' Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
응용 분야
- Holding register in multi-register system
- Strobed register
- General digital logic
C74801 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| 타입 | 세부사항 |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
대체 부품
| MPN | 제조사 | 포장 | 재고 현황 | 단가 | ||
|---|---|---|---|---|---|---|
| CD4043BPWR | TI | TSSOP-16 | 6,121 | $ 0.7921 |



