GSI Technology GS8673ET18BGK-675I

The SigmaDDR-IIIe series SRAM represents the general-purpose I/O portion of the SigmaQuad-IIIe/SigmaDDR-IIIe high-performance SRAM family. While closely resembling the second-generation network SRAM family, the third-generation family introduces new features to support higher operating speeds, including user-configurable on-chip input termination, improved output signal integrity, and adjustable pipeline depth. The GS8673ET18/36BK SigmaDDR-IIIe ECCRAM is a synchronous device that uses differential single-ended master clocks CK and CK̄ to control address and control input registers as well as all output timing. The KD and KD̄ clocks are quasi-differential synchronous input clocks dedicated to controlling the data input registers, allowing the setup and hold window for data inputs to be optimized independently of that for address and control inputs. Each internal read/write operation in the SigmaDDR-IIIe B2 ECCRAM operates at twice the width of the device's I/O bus width. An input data bus demultiplexer accumulates input data before writing to the memory array, while an output data multiplexer captures the data produced by a single read from the memory array and routes it to the appropriate output drivers as needed. Consequently, the address field of the SigmaDDR-IIIe B2 ECCRAM always has one fewer address pin than the nominally indexed depth would suggest. These devices implement an ECC algorithm capable of detecting and correcting all single-bit memory errors, including those caused by soft error rate events, resulting in a projected soft error rate below 0.002 FITs/Mb — an improvement of five orders of magnitude over comparable SRAMs without on-chip ECC. The ECC algorithm uses 5 ECC parity bits to protect every 18 user-visible data bits. The algorithm neither corrects nor detects multi-bit errors; however, its architecture ensures that a single particle strike cannot cause multiple bit errors within a single ECC-protected word.

• On-chip ECC with near-zero soft error rate
• Configurable read latency
• SigmaDDR-IIIe interface supporting simultaneous read/write operations
• General-purpose I/O bus
• Double data rate interface
• Burst length-2 read/write operations
• Pipelined read operations
• Fully coherent read/write pipeline
• Nominal VDD of 1.35 V
• 1.2 V interface compliant with JESD8-16A BIC-3
• 1.5 V HSTL interface
• ZQ pin for programmable output drive impedance
• ZT pin for programmable input termination impedance
• Configurable input termination
• JTAG boundary scan compliant with IEEE 1149.1
• 260-ball, 14 mm × 22 mm, 1 mm ball pitch BGA package
• K: 5/6 RoHS-compliant package
• GK: 6/6 RoHS-compliant package