Alliance Memory AS7C34096A-20JCNTR
| Hersteller | |
| Herst.-Teilenr. | AS7C34096A-20JCNTR |
| LCSC-Nr. | C6862097 |
| Verp. | SOJ-36 |
| Kundennummer | |
| Hauptmerkm. | 4Mbit Parallel Port (Parallel) SOJ-36 Memory RoHS |
| Datenblatt | Alliance Memory AS7C34096A-20JCNTR |
| Alternativteile | 11 |
Produktspezifikationen
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | SOJ-36 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function | |
| Memory Size | 4Mbit | |
| Voltage - Supply | 3V~3.6V;100mA | |
| Access Time | 20ns | |
| Interface | Parallel Port (Parallel) | |
| Standby Supply Current | 8mA |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | SOJ-36 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function |
| Typ | Beschreibung | |
|---|---|---|
| Memory Size | 4Mbit | |
| Voltage - Supply | 3V~3.6V;100mA | |
| Access Time | 20ns | |
| Interface | Parallel Port (Parallel) | |
| Standby Supply Current | 8mA |
Beschreibung
The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Merkmale
- Pin compatible to AS7C34096
- Industrial and commercial temperature
- Organization: 524,288 words x 8 bits
- Center power and ground pins
- High speed - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time
- Low power consumption: ACTIVE - 650 mW / max @ 10 ns
- Low power consumption: STANDBY - 28.8 mW / max CMOS
- Equal access and cycle times
- Easy memory expansion with CE, OE inputs
- TTL-compatible, three-state I/O
- JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2
- ESD protection ≥2000 volts
- Latch-up current ≥200 mA
| Stk. | E-Preis(Nur als Referenz) | Gesamtbetrag |
|---|---|---|
| 1+ | $ 13.9139 | $ 13.91 |
| 200+ | $ 5.5529 | $ 1110.58 |
| 500+ | $ 5.3665 | $ 2683.25 |
| 1,000+ | $ 5.2755 | $ 5275.50 |
Standardgehäuse500/Full Reel | ||
Produktspezifikationen
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | SOJ-36 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function | |
| Memory Size | 4Mbit | |
| Voltage - Supply | 3V~3.6V;100mA | |
| Access Time | 20ns | |
| Interface | Parallel Port (Parallel) | |
| Standby Supply Current | 8mA |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Memory/Memory | |
| Hersteller | Alliance Memory | |
| Verp. | SOJ-36 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function |
| Typ | Beschreibung | |
|---|---|---|
| Memory Size | 4Mbit | |
| Voltage - Supply | 3V~3.6V;100mA | |
| Access Time | 20ns | |
| Interface | Parallel Port (Parallel) | |
| Standby Supply Current | 8mA |
Beschreibung
The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Merkmale
- Pin compatible to AS7C34096
- Industrial and commercial temperature
- Organization: 524,288 words x 8 bits
- Center power and ground pins
- High speed - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time
- Low power consumption: ACTIVE - 650 mW / max @ 10 ns
- Low power consumption: STANDBY - 28.8 mW / max CMOS
- Equal access and cycle times
- Easy memory expansion with CE, OE inputs
- TTL-compatible, three-state I/O
- JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2
- ESD protection ≥2000 volts
- Latch-up current ≥200 mA
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991B2A |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991B2A |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Typ | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
Alternativteile
| MPN | Hersteller | Verpackung | Verfügbarkeit | Stückpreis | ||
|---|---|---|---|---|---|---|
| AS7C34096A-20JCN | Alliance Memory | SOJ-36 | 0 | $ 5.5751 | ||
| AS7C34096A-20JIN | Alliance Memory | SOJ-36 | 0 | $ 6.9153 | ||
| AS7C34096A-20JINTR | Alliance Memory | SOJ-36 | 0 | $ 5.3561 | ||
| CY7C1049BV33-20VCT | Infineon/CYPRESS | BSOJ-36 | 0 | $ 0.3593 | ||
| AS7C34096A-10JCN | Alliance Memory | SOJ-36 | 0 | $ 5.5279 | ||
| AS7C34096A-15JCN | Alliance Memory | SOJ-36 | 0 | $ 5.2957 | ||
| AS7C34096A-12JCNTR | Alliance Memory | SOJ-36 | 0 | $ 5.0922 | ||
| AS7C34096A-10JCNTR | Alliance Memory | SOJ-36 | 0 | $ 4.8298 | ||
| AS7C34096A-15JCNTR | Alliance Memory | SOJ-36 | 0 | $ 11.5747 | ||
| CY7C1049BV33-12VCT | Infineon/CYPRESS | BSOJ-36 | 0 | $ 0.4192 | ||
| CY7C1049BV33-12VC | Infineon/CYPRESS | BSOJ-36 | 0 | $ 0.8365 |

