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ADI ADSP-BF561SKBCZ500

Hersteller
Herst.-Teilenr.
ADSP-BF561SKBCZ500
LCSC-Nr.
C659918
Verp.
BGA-256
Kundennummer
Hauptmerkm.
Fixed-point 500MHz BGA-256 DSP (Digital Signal Processors) RoHS
DatenblattADI ADSP-BF561SKBCZ500
RoHS-Konformität1 Dokumente verfügbar
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Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
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Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 35.4304$ 35.43
200+$ 13.7122$ 2742.44
500+$ 13.2307$ 6615.35
1,000+$ 12.9914$ 12991.40
Standardgehäuse189/Full Tray
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$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors)
HerstellerADI
Verp.BGA-256
TypeFixed-point
Operating Temperature0℃~+70℃
Clock Rate500MHz

Beschreibung

KI-Übersetzung

The ADSP-BF561 processor is a high performance member of the Blackfin family of products targeting a variety of multimedia, industrial, and telecommunications applications. At the heart of this device are two independent Analog Devices Blackfin processors. These Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantage of a clean, orthogonal RISC-like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities in a single instruction set architecture. The ADSP-BF561 processor has 328K bytes of on-chip memory. Each Blackfin core includes: • 16K bytes of instruction SRAM/cache • 16K bytes of instruction SRAM • 32K bytes of data SRAM/cache • 32K bytes of data SRAM • 4K bytes of scratchpad SRAM Additional on-chip memory peripherals include: • 128K bytes of low latency on-chip L2 SRAM • Four-channel internal memory DMA controller • External memory controller with glueless support for SDRAM, mobile SDRAM, SRAM, and flash.

Merkmale

KI-Übersetzung
  • Dual symmetric 600 MHz high performance Blackfin cores
  • 328K bytes of on-chip memory
  • Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support
  • Advanced debug, trace, and performance monitoring
  • Wide range of operating voltages
  • 256-ball CSP_BGA (2 sizes) and 297-ball PBGA package options
  • Dual 12-channel DMA controllers (supporting 24 peripheral DMAs)
  • 2 memory-to-memory DMAs
  • 2 internal memory-to-memory DMAs and 1 internal memory DMA controller
  • 12 general-purpose 32-bit timers/counters with PWM capability
  • SPI-compatible port
  • UART with support for IrDA
  • Dual watchdog timers
  • Dual 32-bit core timers
  • 48 programmable flags (GPIO)
  • On-chip phase-locked loop capable of 0.5× to 64× frequency multiplication
  • 2 parallel input/output peripheral interface units supporting ITU-R 656 video and glueless interface to analog front end ADCs
  • 2 dual channel, full duplex synchronous serial ports supporting eight stereo I²S channels

Anwendungen

KI-Übersetzung
  • Multimedia
  • Industrial
  • Telecommunications