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ADI AD9633BCPZ-105

Produttore
Cod. Prod.
AD9633BCPZ-105
Cod. LCSC
C653650
Imballo
LFCSP-48(7x7)
Numero Cliente
Attr. chiave
Serial port 1.8V LFCSP-48(7x7) Analog to Digital Converters (ADC) RoHS
Scheda TecnicaADI AD9633BCPZ-105
Conformità RoHS1 documenti disponibili
Parti alternative4
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 220.8783$ 220.88
200+$ 85.4774$ 17095.48
500+$ 82.4738$ 41236.90
1,000+$ 80.989$ 80989.00
Package Standard260/Full Tray
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ProduttoreADI
ImballoLFCSP-48(7x7)
Operating Temperature-40℃~+85℃
InterfaceSerial port
Quiescent Current (Iq)-
Voltage - Supply1.8V
Number of Channels4
Integral non - linearity1.4LSB
Voltage ReferenceBuilt-in
Clock/OscillatorExternal
Clock Frequency10MHz~1GHz
FeaturesMulti-chip synchronization;Programmable output clock and data alignment;Programmable output resolution
Resolution(Bits)105MHz;12
S/N Ratio71.7dB
DNL (LSB)0.3LSB
ADC architecture-
Programmable GainNot supported

Descrizione

Traduzione AI

A quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of -40°C to +85°C.

Caratteristiche

Traduzione AI
  • 1.8 V supply operation
  • Low power: 100 mW per channel at 125 MSPS with scalable power options
  • SNR = 71 dB (to Nyquist)
  • SFDR = 91 dBc (to Nyquist)
  • DNL = ±0.3 LSB (typical); INL = ±0.5 LSB (typical)
  • Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3)
  • 650 MHz full power analog bandwidth
  • 2 V p-p input voltage range
  • Serial port control
  • Full chip and individual channel power-down modes
  • Flexible bit orientation
  • Built-in and custom digital test pattern generation
  • Multichip sync and clock divider
  • Programmable output clock and data alignment
  • Programmable output resolution
  • Standby mode

Applicazioni

Traduzione AI
  • Medical ultrasound
  • High speed imaging
  • Quadrature radio receivers
  • Diversity radio receivers
  • Test equipment

Parti alternative

MPNProduttoreImballaggioDisponibilitàPrezzo unitario
AD9633BCPZRL7-125ADILFCSP-48(7x7)0$ 261.7972
AD9633BCPZ-125ADILFCSP-48(7x7)0$ 261.7972
AD9633BCPZRL7-105ADILFCSP-48(7x7)0$ 220.8783
AD9633BCPZ-80ADILFCSP-48(7x7)0$ 68.7214