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MICROCHIP KSZ8864CNXI-TR

Hersteller
MICROCHIP
Herst.-Teilenr.
KSZ8864CNXI-TR
LCSC-Nr.
C631679
Verp.
QFN-64-EP(8x8)
Kundennummer
Hauptmerkm.
Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
DatenblattMICROCHIP KSZ8864CNXI-TR
RoHS-Konformität2 Dokumente verfügbar
Vorrätig: 5
5 Ab Lager, sofort versandfertig
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
Stk.E-PreisGesamtbetrag
1+$ 10.1933$ 10.19
10+$ 9.8658$ 98.66
Standardgehäuse1000/Full Reel
Besserer Preis bei größerer Menge?
$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Interface/Controllers
HerstellerMICROCHIP
Verp.QFN-64-EP(8x8)
Voltage - Supply1.8V;2.5V;3.3V
FeaturesPower-up/reset configuration;Non-volatile configuration storage;Interrupt generation
Operating Temperature-40℃~+85℃
InterfaceSPI;I2C
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KI-Übersetzung
  • Advanced Switch Features
    • IEEE 802.1q VLAN Support for up to 128 VLAN Groups (Full-Range 4096 of VLAN IDs)
    • Static MAC Table Supports up to 32 Entries
    • VLAN ID Tag/Untagged Options, Per Port Basis
    • IEEE 802.1 p/q Tag Insertion or Removal on a Per Port Basis Based on Ingress Port (Egress)
    • Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis
    • Jitter-Free Per Packet Based Rate Limiting Support
    • Broadcast Storm Protection with Percentage Control (Global and Per Port Basis)
    • IEEE 802.1d Rapid Spanning Tree Protocol RSTP Support
    • Tail Tag Mode (1 Byte Added Before FCS) Support at Port 4 to Inform the Processor Which Ingress Port Receives the Packet
    • 1.4 Gbps High-Performance Memory Bandwidth and Shared Memory Based Switch Fabric with Fully Non-Blocking Configuration
    • Dual MII/RMII with MAC 3 SW3-MII/RMII and MAC 4 SW4-MII/RMII Interfaces
    • Enable/Disable Option for Huge Frame Size up to 2000 Bytes Per Frame
    • IGMP v1/v2 Snooping (IPv4) Support for Multicast Packet Filtering
    • IPv4/IPv6 QoS Support
    • Support Unknown Unicast/Multicast Address and Unknown VID Packet Filtering
    • Self-Address Filtering
  • Comprehensive Configuration Register Access
    • Serial Management Interface (MDC/MDIO) to All PHYs Registers High-Speed SPI (up to 25 MHz) and I²C Master Interface to all Internal Registers
    • I/O Pins Strapping and EEPROM to Program Selective Registers in Unmanaged Switch Mode Control Registers Configurable on the Fly (Port-Priority, 802.1p/d/q, AN…)
  • QoS/CoS Packet Prioritization Support
    • Per Port, 802.1p and DiffServ-Based
    • 1/2/4-Queue QoS Prioritization Selection
    • Programmable Weighted Fair Queuing for Ratio Control
    • Re-Mapping of 802.1p Priority Field Per Port Basis
  • Integrated 4-Port 10/100 Ethernet Switch
    • Next Generation Switch with Four MACs and Two PHYs that are Fully Compliant with the IEEE 802.3u Standard
    • Non-Blocking Switch Fabric Ensures Fast Packet Delivery by Utilizing a 1K MAC Address Lookup Table and a Store-and-Forward Architecture
    • On-Chip 64Kbyte Memory for Frame Buffering (Not Shared with 1K Unicast Address Table)
    • Full-Duplex IEEE 802.3x Flow Control (PAUSE) with Force Mode Option
    • Half-Duplex Back Pressure Flow Control
    • HP Auto MDI/MDI-X and IEEE Auto Crossover Support
    • LinkMD TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
    • MII Interface of MAC Supports Both MAC Mode and PHY Mode
    • Per Port LED Indicators for Link, Activity, and 10/ 100 Speed
    • Register Port Status Support for Link, Activity, Full-/Half-Duplex and 10/100 Speed
    • On-Chip Terminations and Internal Biasing Technology for Cost Down and Lowest Power Consumption
  • Switch Monitoring Features
    • Port Mirroring/Monitoring/Sniffing: Ingress and/or Egress Traffic to Any Port or MII/RMII
    • MIB Counters for Fully Compliant Statistics Gathering 34 MIB Counters Per Port
    • Loopback Support for MAC, PHY, and Remote Diagnostic of Failure
    • Interrupt for the Link Change on Any Ports
  • Low-Power Dissipation
    • Full-Chip Software Power-Down and Per Port Software Power-Down
    • Energy-Detect Mode Support < 0.1 W Full-Chip Power Consumption When All Ports Have No Activity
    • Very-Low Full-Chip Power Consumption (~ 0.3W), without Extra Power Consumption on Transformers
    • Dynamic Clock Tree Shutdown Feature
    • Voltages: - Analog VDDAT 3.3V Only - VDDIO Support 3.3V, 2.5V, and 1.8V - Low 1.2V Core Power
    • Commercial Temperature Range: 0°C to +70°C
    • Industrial Temperature Range: -40°C to +85°C
    • Automotive AEC-Q100 Grade 3 Temperature Range: -40°C to +85°C
    • Available in 64-pin QFN, Lead-Free Small Package

Anwendungen

KI-Übersetzung
  • VoIP Phone
  • Set-Top/Game Box
  • Automotive Ethernet
  • Industrial Control
  • IPTV POF
  • SOHO Residential Gateway
  • Broadband Gateway/Firewall/VPN
  • Integrated DSL/Cable Modem
  • Wireless LAN Access Point + Gateway
  • Standalone 10/100 Switch
  • Embedded System