Infineon S26HS01GTGABHA033

This product family consists of high-speed CMOS NOR flash memory devices compliant with the JEDEC JESD251 extended SPI specification. Designed for functional safety, they are developed in accordance with the ISO 26262 standard to achieve ASIL-B compliance and ASIL-D readiness. Both HyperBus and legacy SPI interfaces are supported. Both interfaces transmit transactions serially, reducing the number of interface connection signals. SPI supports single data rate, while HyperBus supports double data rate. The HyperBus interface transfers two data bytes per clock cycle on the data signals. Read or program/write accesses consist of a series of 16-bit wide, single-clock-cycle data transfers. Read and program/write operations are burst-oriented. Read transactions can specify either wrap or linear burst mode. During wrap operation, access begins at the selected location and continues in a group wrap sequence within a configured number of locations. During linear operation, access begins at the selected location and continues sequentially until the read operation is terminated. Write transactions transfer one or more 16-bit values. Each random read access covers a 32-byte row.

• Cypress 45nm MirrorBit® technology, 2 bits stored per memory array cell
• Uniform and hybrid sector architecture options
• 256- or 512-byte page program buffer
• 1024-byte (32×32 bytes) one-time programmable Security Silicon Region (SSR)
• HyperBus™ interface and legacy (x1) SPI support, compliant with JEDEC xSPI (JESD251) specification
• Functional safety: industry-first NOR flash compliant with ISO 26262 ASIL B and ASIL D ready
• EnduraFlex™ architecture with high-endurance and long-retention partitions
• Interface CRC detects communication errors between host controller and Semper™ flash device
• Data integrity CRC detects errors in storage array
• SafeBoot reports device initialization failures, detects configuration corruption, and provides recovery options
• Built-in ECC corrects single-bit errors and detects double-bit errors in memory array data (SECDED)
• Sector erase status indicator for power loss during erase
• Advanced sector protection at individual memory array sector granularity
• AutoBoot enables immediate memory array access after power-up
• Hardware reset via CS# signal method (JEDEC) and dedicated RESET# pin
• Serial Flash Discoverable Parameters (SFDP) describing device capabilities and features
• Device ID, manufacturer ID, and unique ID
• Minimum program-erase cycle count varies by device density
• 4 KB sector minimum program-erase cycle count: 300,000
• Data retention: minimum 25 years
• Supply voltage: 1.7–2.0 V (HS-T) and 2.7–3.6 V (HL-T)
• Temperature ranges: Industrial (−40°C to +85°C), Industrial Plus (−40°C to +105°C), Automotive AEC-Q100 Grade 3 (−40°C to +85°C), Automotive AEC-Q100 Grade 2 (−40°C to +105°C), Automotive AEC-Q100 Grade 1 (−40°C to +125°C)
• 256 Mb and 512 Mb in 24-ball BGA 6×8 mm package; 1 Gb in 24-ball BGA 8×8 mm package