Intel/Altera EP4CE10F17A7N

Cyclone series FPGAs are based on a 1.5V, 0.13μm all-layer copper SRAM process, offering densities up to 20,060 logic elements (LEs) and RAM capacity up to 288K bits. These devices feature PLLs for clock management and dedicated DDR interfaces to support DDR SDRAM and Fast Cycle RAM (FCRAM) memory requirements, providing a cost-effective solution for data path applications. Cyclone devices support multiple I/O standards, including LVDS at data rates up to 311Mbps and 66MHz, 32-bit PCI, enabling interfacing and support with ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices for programming Cyclone devices. Cyclone devices employ a two-dimensional row- and column-based architecture for implementing custom logic. Column and row interconnects provide signal routing at varying speeds for connections between LABs and embedded memory blocks. The logic array consists of LABs, each containing 10 LEs. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). I/O pins on each Cyclone device are driven by IOEs located at the ends of LAB rows and columns along the device periphery. I/O pins support a variety of single-ended and differential I/O standards. Cyclone devices provide a global clock network and up to two PLLs.

• 2,910 to 20,060 logic elements (LEs)
• Up to 294,912 bits of RAM (36,864 bytes)
• Configuration support via low-cost serial configuration devices
• LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standard support
• 66MHz, 32-bit PCI standard support
• Low-speed (311Mbps) LVDS I/O support
• Up to two PLLs per device for clock multiplication and phase shifting
• Up to eight global clock lines with six clock resources per logic array block (LAB) row
• External memory support including DDR SDRAM (133MHz), FCRAM, and single data rate (SDR) SDRAM
• Multiple IP core support including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions