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Nexperia 74LVC3G04GT,115

Produttore
Nexperia
Cod. Prod.
74LVC3G04GT,115
Cod. LCSC
C548743
Imballo
XSON-8(1x2)
Numero Cliente
Attr. chiave
Schmitt trigger 1.65V~5.5V 3.2ns@5V,50pF 4uA 3 XSON-8(1x2) Gates and Inverters RoHS
Scheda TecnicaNexperia 74LVC3G04GT,115
Conformità RoHS1 documenti disponibili
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 0.0551$ 0.06
10+$ 0.0437$ 0.44
30+$ 0.0381$ 1.14
100+$ 0.0338$ 3.38
500+$ 0.0304$ 15.20
1,000+$ 0.0287$ 28.70
Package Standard5000/Full Reel
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Logic/Gates and Inverters
ProduttoreNexperia
ImballoXSON-8(1x2)
Input TypeSchmitt trigger
Logic Family74LVC
Voltage - Supply1.65V~5.5V
Output Logic Level - Low-
Propagation Delay3.2ns@5V,50pF
FeaturesPower shutdown protection;Noise suppression function
Input Logic Level - Low-
Operating Temperature-40℃~+125℃
Input Logic Level - High1.7V~2V
Output Logic Level - High-
Quiescent Current(Iq)4uA
Current - Output High(IOH)32mA
Number of Channels3
Current - Output Low(IOL)32mA
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Descrizione

Traduzione AI

The 74LVC3G04 is a triple inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Caratteristiche

Traduzione AI
  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant outputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard: JESD8 - 7 (1.65 V to 1.95 V) JESD8 - 5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V)
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch - up performance exceeds 250 mA
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power - down mode operation
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS - 001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS - 002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from - 40 ℃ to + 85 ℃ and - 40 ℃ to + 125 ℃

Applicazioni

Traduzione AI
  • Level translation in mixed 3.3V and 5V environments
  • High noise immunity
  • Direct TTL-level interface
  • Partial power-down mode operation