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Infineon SAK-TC1798F-512F300EP AB

Produttore
Infineon
Cod. Prod.
SAK-TC1798F-512F300EP AB
Cod. LCSC
C538745
Imballo
PG-LFBGA-516
Numero Cliente
Attr. chiave
TriCore 32 Bit 300MHz PG-LFBGA-516 Microcontrollers
Scheda TecnicaInfineon SAK-TC1798F-512F300EP AB
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 62.9875$ 62.99
200+$ 24.3761$ 4875.22
500+$ 23.5194$ 11759.70
1,000+$ 23.0965$ 23096.50
Package Standard500/Full Reel
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Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProduttoreInfineon
ImballoPG-LFBGA-516
ADC (Bit)12bit
Number of I/O238
Operating Temperature-40℃~+125℃
Voltage - Supply1.235V~1.365V;3.135V~3.63V;3.135V~5.5V
Program Memory TypeFLASH
CPU CoreTriCore
Program Storage Size4MB
EEPROM192KB
Core Size32 Bit
CPU Maximum Speed300MHz
Oscillator TypeBuilt-in+External
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Caratteristiche

Traduzione AI
  • High-performance 32-bit super-scalar TriCore V1.6 CPU with 6-stage pipeline
  • Superior real-time performance
  • Strong bit handling
  • Fully integrated DSP capabilities
  • Multiply-accumulate unit able to sustain 2 MAC operations per cycle
  • Fully pipelined Floating point unit (FPU)
  • 300 MHz operation at full temperature range
  • 32-bit Peripheral Control Processor with single cycle instruction (PCP2)
  • 16 Kbyte Parameter Memory (PRAM)
  • 32 Kbyte Code Memory (CMEM)
  • 200 MHz operation at full temperature range
  • Multiple on-chip memories
  • 4 Mbyte Program Flash Memory (PFLASH) with ECC
  • 192 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
  • 2 x 8 Kbyte Key Flash
  • 128 Kbyte Data Scratch-Pad RAM (DSPR)
  • 16 Kbyte Instruction Cache (ICACHE)
  • 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
  • 16 Kbyte Data Cache (DACHE)
  • 128 Kbyte Memory (SRAM)
  • 16 Kbyte BootROM (BROM)
  • 16-Channel DMA Controller
  • 8-Channel Safe DMA (SDMA) Controller
  • Sophisticated interrupt system with 2x255 hardware priority arbitration levels serviced by CPU or PCP2
  • High performing on-chip bus structure
  • 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
  • 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
  • One bus bridge (SFI Bridge)
  • Versatile On-chip Peripheral Units
  • Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection
  • Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction
  • Four SSC Guardian (SSCG) modules, one for each SSC
  • Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
  • Two High-Speed Micro Link interfaces (MLI) for serial inter-processor communication
  • One External Bus Interface (EBU) supporting different memories: asynchronous memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0 (limited frequency at 1.8 V I/O supply)
  • One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality)
  • One FlexRayTM module with 2 channels (E-Ray)
  • Two General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2)