TI CD4518BNSR

CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchro. nous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high tevels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.

• Medium-spced operation -- 6-MHz typical clock frequency at 10 V.
• Positive- or negative-edge triggering
• Synchronous internaf carry propagation
• 100% tested for quiescent curren't at 20 V
• Maximum input current of μA at 18 V over fult package-temperature range; 100 nA at 18 V and 25℃
• Noise rmargin(over full package-temperature range): 1V at VDD = 5 V; 2V at VDD = 10 V; 2.5 V at VDD = 15 V
• 5-V, 10V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 48 Series CMOS Devices"

• Multistage synchronous counting
• Multistage ripple counting
• Frequency dividers