RENESAS 82V3398NLG

The IDT82V3398 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EECOption1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device consists of a highly quality and configurable DPLL to provide system clock for node timing synchronization within a SONET / SDH / Synchronous Ethernet network. An input clock is automatically or manually selected for the DPLL. The DPLL has three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. There is also a high performance APLL that is used for low jitter SONET and Ethernet Clocks The device provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz. Different settings cover all SONET / SDH clock synchronization requirements. A highly stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a microprocessor interface. The device supports I2C and serial microprocessor interface modes. In general, the device can be used in Master/Slave application. In this application, two devices should be used together to enable system protection against single chip failure.

• Features 0.5 mHz to 560 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
• Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) jitter generation requirements
• Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
• Provides clocks for 1 Gigabit and 10 Gigabit Ethernet application
• It supports clock generation for IEEE-1588 applications
• Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option 1 and EEC-Option 2 Clocks
• Provides SONET clocks with less than 1.5 ps of RMS Phase Jitter (12 kHz - 20 MHz)
• Supports 1 pps input and output
• Employs PLL architecture to feature excellent jitter performance and minimize the number of the external components
• Supports programmable DPLL bandwidth from 0.5 mHz to 560 Hz
• Supports 1.1×10⁻⁵ ppm absolute holdover accuracy and 4.4×10⁻⁸ ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients on the DPLL output to be no more than 0.61 ns
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Provides OUT1~OUT6 output clocks whose frequencies cover from 1 Hz (1PPS) to 644.53125 MHz
• 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1, N x T1, N x 13.0 MHz, N x 3.84 MHz, 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 25MHz, 25.78125 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz or 156.25 MHz or 161.1328125 MHz for CMOS outputs
• 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1, N x T1, N x 13.0 MHz, N x 3.84 MHz, 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz, 156.25 MHz, 161.1328125 MHz, 311.04 MHz, 312.5 MHz, 322.265625 MHz, 622.08 MHz, 625 MHz or 644.53125 MHz for differential Outputs
• Provides IN1~IN6 input clocks whose frequencies cover from 1 Hz (1PPS) to 625 MHz
• 1PPS, 2 kHz, 4 kHz, N x 8 kHz, 1.544 MHz, 2.048 MHz, 6.25 MHz, 6.48MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 125MHz, 155.52 MHz or 156.25 MHz for CMOS inputs
• 1PPS, 2 kHz, 4 kHz, N x 8 kHz, 1.544 MHz, 2.048 MHz, 6.25 MHz, 6.48 MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 125MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz for differential inputs
• Internal DCO can be controlled by an external processor to be used for IEEE-1588 clock generation
• Supports Forced or Automatic operating mode switch controlled by an internal state machine. It supports Free - Run, Locked and Holdover modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock failure
• Provides a 2 kHz, 4 kHz, 8 kHz, or 1PPS frame sync input signal, and a 2 kHz, 8 kHz, or 1PPS frame sync output signals
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports PECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Master/Slave application (two chips used together) to enable system protection against single chip failure
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recommendations
• I2C and Serial microprocessor interface modes
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 72-pin QFN package, Green package options available

• 1 Gigabit Ethernet and 10 Gigabit Ethernet
• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipments
• Synchronous Ethernet equipments
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• IP and ATM core switches and access equipments
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipments