AMD/XILINX XCR3032XL-10CS48I
| Produttore | |
| Cod. Prod. | XCR3032XL-10CS48I |
| Cod. LCSC | C1521391 |
| Imballo | CSBGA-48 |
| Numero Cliente | |
| Attr. chiave | CSBGA-48 FPGAs (Field Programmable Gate Array) |
| Scheda Tecnica | AMD/XILINX XCR3032XL-10CS48I |
Specifiche del Prodotto
Tutto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX | |
| Imballo | CSBGA-48 |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX |
| Tipo | Descrizione | |
|---|---|---|
| Imballo | CSBGA-48 |
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Descrizione
Traduzione AI
The CoolRunner XPLA3 XCR3032XL device is a 3.3V CPLD with 32 macrocells, suitable for designs that are power-sensitive and require cutting-edge programmable logic solutions. A total of two function blocks provide 750 available gates. The fastest pin-to-pin propagation delay can reach 4.5 ns, and the maximum system frequency is 213 MHz.
Caratteristiche
Traduzione AI
- Low-power 3.3V, 32-macrocell CPLD
- 4.5 ns pin-to-pin logic delay
- System frequency up to 213 MHz
- 32 macrocells, 750 usable gates
- Small form factor packages: 48-ball CS BGA (36 user I/O pins), 44-pin VQFP (36 user I/O)
- Optimized for 3.3V systems
- Ultra-low power operation
- Typical standby current of 17 μA at 25°C
- 3.3V core supply with 5V-tolerant I/O pins
- Advanced 0.35-micron five-layer metal EEPROM process
- Fast Zero-Power (FZP) CMOS technology
- 3.3V PCI electrical specification compatible outputs (no internal clamp diodes on any input or I/O, no minimum clock input capacitance)
- In-system programmable
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Pin-locking on design changes
- Fully compliant with IEEE Standard 1149.1 boundary scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
- JTAG ISP pins with dual-function port enable pin
- Supply voltage 2.7V to 3.6V over industrial temperature range
- Per-macrocell programmable slew rate control
- Security bit to prevent unauthorized access
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
| Qtà | Pr. unit.(Solo per riferimento) | Importo totale |
|---|---|---|
| 1+ | $ 6.0533 | $ 6.05 |
| 200+ | $ 2.3434 | $ 468.68 |
| 416+ | $ 2.2609 | $ 940.53 |
| 832+ | $ 2.2197 | $ 1846.79 |
Package Standard416/Full Tray | ||
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Specifiche del Prodotto
Tutto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX | |
| Imballo | CSBGA-48 |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX |
| Tipo | Descrizione | |
|---|---|---|
| Imballo | CSBGA-48 |
Aiuto & FeedbackMostra prodotti simili (0) >
Descrizione
Traduzione AI
The CoolRunner XPLA3 XCR3032XL device is a 3.3V CPLD with 32 macrocells, suitable for designs that are power-sensitive and require cutting-edge programmable logic solutions. A total of two function blocks provide 750 available gates. The fastest pin-to-pin propagation delay can reach 4.5 ns, and the maximum system frequency is 213 MHz.
Caratteristiche
Traduzione AI
- Low-power 3.3V, 32-macrocell CPLD
- 4.5 ns pin-to-pin logic delay
- System frequency up to 213 MHz
- 32 macrocells, 750 usable gates
- Small form factor packages: 48-ball CS BGA (36 user I/O pins), 44-pin VQFP (36 user I/O)
- Optimized for 3.3V systems
- Ultra-low power operation
- Typical standby current of 17 μA at 25°C
- 3.3V core supply with 5V-tolerant I/O pins
- Advanced 0.35-micron five-layer metal EEPROM process
- Fast Zero-Power (FZP) CMOS technology
- 3.3V PCI electrical specification compatible outputs (no internal clamp diodes on any input or I/O, no minimum clock input capacitance)
- In-system programmable
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Pin-locking on design changes
- Fully compliant with IEEE Standard 1149.1 boundary scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
- JTAG ISP pins with dual-function port enable pin
- Supply voltage 2.7V to 3.6V over industrial temperature range
- Per-macrocell programmable slew rate control
- Security bit to prevent unauthorized access
C1521391 Libreria EasyEDA
Conformità & Codici di Esportazione
| Tipo | Dettagli |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Tipo | Dettagli |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Tipo | Dettagli |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |

