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MICROCHIP MEC1521H-B0-I/SZ

Hersteller
MICROCHIP
Herst.-Teilenr.
MEC1521H-B0-I/SZ
LCSC-Nr.
C1016345
Verp.
WFBGA-144
Kundennummer
Hauptmerkm.
ARM Cortex-M4 WFBGA-144 Application Specific Microcontrollers RoHS
DatenblattMICROCHIP MEC1521H-B0-I/SZ
RoHS-Konformität2 Dokumente verfügbar
Nicht vorrätig
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Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
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Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 5.0873$ 5.09
260+$ 1.9695$ 512.07
520+$ 1.9001$ 988.05
1,040+$ 1.8661$ 1940.74
Standardgehäuse260/Full Tray
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Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Embedded/Application Specific Microcontrollers
HerstellerMICROCHIP
Verp.WFBGA-144
Voltage - Supply1.71V~3.465V
Operating Temperature-40℃~+85℃
CPU CoreARM Cortex-M4
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KI-Übersetzung
  • Operating Voltages: 3.3 V and 1.8 V
  • Operating Temperature Range: -40 ℃ to 85 ℃
  • Chip is designed to always operate in Lowest Power state during Normal Operation
  • Supports all 5 ACPI Power States for PC platforms
  • Supports 2 Chip-level Sleep Modes: Light Sleep and Heavy Sleep
  • Low Standby Current in Sleep Modes
  • Programmable clock frequency up to 48 MHz
  • Fixed point processor
  • Single 4GByte Addressing Space
  • Nested Vectored Interrupt Controller (NVIC)
  • Maskable Interrupt Controller
  • Maskable hardware wake up events
  • 8 Levels of priority, individually assignable by vector
  • EC Interrupt Aggregator expands number of Interrupt sources supported or reduces number of vectors needed
  • Complete ARM Standard debug support
  • JTAG-Based DAP port, comprised of SWJDP and AHB-AP debugger access functions
  • 256 KB Code/Data SRAM
  • 224 KB optimized for code performance
  • 32 KB optimized for data performance
  • 64 Bytes Battery Powered Storage SRAM
  • 4K bits OTP
  • In circuit programmable
  • ROM
  • Contains Boot ROM
  • Contains Runtime APIs for built-in functions
  • 2K byte Internal EEPROM (MEC1523 Only)
  • 4Mbit in-chip SPI Serial Flash (MEC1527 only)
  • SST25PF040C
  • SPI Master controller
  • Supports Mode 0 and mode 3
  • 24MHz
  • 48 MHz Internal PLL
  • 32 kHz Clock Sources
  • Internal 32 kHz silicon oscillator
  • External 32 kHz crystal (XTAL) source
  • External single-ended 32 kHz clock source
  • Boot ROM Secure Boot Loader
  • Hardware Root of Trust (RoT) using Secure Boot and Immutable Code using ECDSA p384 and SHA-384
  • Supports 2 Code Images in external SPI Flash (Primary and Fall back image)
  • Supports Full EC firmware redundancy over Two Flash components
  • Authenticates SPI Flash image before loading
  • Support AES-256 Encrypted SPI Flash images
  • Key Revocation
  • Roll back protection up to 128 Revisions
  • Hardware Accelerators:
  • Multi purpose AES Crypto Engine:
  • Support for 128-bit - 256-bit key length
  • Supports Battery Authentication applications
  • Digital Signature Algorithm Support
  • Support for ECDSA and EC_KCDSA
  • Cryptographic Hash Engine
  • Support for SHA-1, SHA-256 to SHA-512
  • Public Key Crypto Engine
  • Hardware support for RSA and Elliptic Curve asymmetric public key algorithms
  • RSA keys length of 1024 to 4096 bits
  • ECC Prime Field keys up to 571 bits
  • ECC Binary Field keys up to 571 bits
  • Microcoded support for standard public key algorithms
  • OTP for storing Keys and IDs
  • Lockable on 32 B boundaries to prevent read access or write access
  • True Random Number Generator
  • 1 kbit FIFO
  • JTAG Disabled by default
  • Enhanced Serial Peripheral Interface (eSPI)
  • Intel eSPI Specification compliant
  • eSPI Interface Base Spec, Intel Doc. #327432-004, Rev. 1.0.MEC152x
  • eSPI Compatibility Spec, Intel Doc. #562633, Rev. 0.6
  • Support for Master Attached Flash Sharing (MAFS)
  • Support for Slave Attached Flash Sharing (SAFS)
  • Supports all four channels:
  • Peripheral Channel
  • Virtual Wires Channel
  • Out-of-Band (OOB) Tunneled Message Channel
  • Run-time Flash Access Channel
  • Supports EC Bus Master to Host Memory
  • Supports up to 66 MHz maximum operating frequency
  • One Serial Peripheral Interface (SPI) Slave
  • Quad SPI (half-duplex) or Single wire (full duplex) support
  • Mode 0 and Mode3 operation
  • Programmable wait time for response delay
  • System to EC Message Interface
  • Two Embedded Memory Interfaces
  • Provides Two Windows to On-Chip SRAM for Host Access
  • Two Register Mailbox Command Interface
  • Mailbox Registers Interface
  • Thirty-two 8-bit registers
  • Two Register Mailbox Command Interfaces
  • Two Register SMI Source Interfaces
  • Five ACPI Embedded Controller Interfaces
  • Four EC Interfaces
  • One Power Management Interface
  • One Serial Peripheral Interface (SPI) Master Controller
  • Dual and Quad I/O Support
  • Flexible Clock Rates
  • Support for 1.8V and 3.3V slave devices
  • SPI Burst Capable
  • SPI Controller Operates with Internal DMA Controller with CRC Generation
  • Mappable to the following ports (only 1 port active at a time)
  • 1 shared SPI Interface
  • 1 Private SPI interface
  • 1 General Purpose SPI interface
  • 1 In-Chip SPI (MEC1527 Only)
  • 8042 Emulated Keyboard Controller
  • 8042 Style Host Interface
  • Port 92 Legacy A20M Support
  • Fast GATEA20 & Fast CPU_RESET
  • 18x8 Interrupt Capable Multiplexed Keyboard Scan Matrix
  • Optional Push-Pull Drive for Fast Signal Switching
  • PECI Interface 3.1
  • Support Intel’s low voltage PECI
  • Port 80 BIOS Debug Port
  • Two Ports, Assignable to Any eSPI IO Address
  • 24-bit Timestamp with Adjustable Timebase
  • 16-Entry FIFO
  • Internal DMA Controller
  • Hardware or Firmware Flow Control
  • Firmware Initiated Memory-to-Memory transfers
  • Hardware CRC-32 Generator on Channel 0
  • 12-Hardware DMA Channels support five SMBus Master/Slave Controllers and One SPI Controller
  • I2C/SMBus Controllers
  • 5 I2C/SMBus controllers
  • 3 I2C only controllers without the Network layer
  • Up to 16 Configurable I2C ports
  • Full Crossbar switch allows any port to be connected to any controller
  • Supports Promiscuous mode of operation
  • Fully Operational on Standby Power
  • Multi-Master Capable
  • Supports Clock Stretching
  • Programmable Bus Speeds
  • 1 MHz Capable
  • Supports DMA Network Layer
  • General Purpose I/O Pins
  • Inputs
  • Asynchronous rising and falling edge wakeup detection
  • Interrupt High or Low Level
  • Outputs:
  • Push Pull or Open Drain output
  • Programmable power well emulation
  • Pull up or pull down resistor control
  • Automatically disabling pull-up resistors when output driven low
  • Automatically disabling pull-down resistors when output driven high
  • Programmable drive strength