Takeaway
- Micro PCB: laser-drilled, ≤150 µm finished diameter, aspect ratio ≤1:1 per IPC-2226 — connects adjacent layers only.
- VIPPO (Via-in-Pad Plated Over): copper-filled via under BGA pad, planarized to ±10 µm — mandatory for BGA pitch ≤0.4 mm.
- 01005 components (0.4×0.2 mm, ~0.04 mg) require Type 4/5 solder paste, electroformed stencils, and ±30 µm @3σ placement accuracy.
- Tombstoning root cause: asymmetric surface tension when one solder joint melts before the other — prevented by symmetric NSMD pads, balanced paste volume (3D SPI Cpk ≥1.33), and controlled soak at 180–200°C.
- BGA inspection chain: 3D SPI → 3D AOI → AXI (<5 µm resolution). IPC-7095 limits void area to ≤25 % per ball (Class 2).
- HDI stack-up options: 1+N+1 (0.5 mm BGA), 2+N+2 (0.4 mm BGA), 3+N+3/Any-Layer (0.25–0.3 mm micro-BGA).
- Supplier certifications to require: IPC-A-600/6012 Class 3, IPC-A-610 Class 3, IPC-7095, ISO 9001. Add IATF 16949 for automotive; ISO 13485 for medical.
What Are Micro PCB/SMT Technologies?
“Micro” in PCB and SMT contexts covers a family of interconnected miniaturization technologies spanning three principal domains: micro components (passive and active SMD packages at 0201/01005 scale and below), microvia PCBs (HDI boards using laser-drilled interconnects with diameter ≤150 µm per IPC-2226), and micro-pitch assembly services (SMT lines capable of placing fine-pitch BGA, QFN, CSP, and chip components with sub-30 µm placement accuracy). Together these technologies form the enabling foundation for modern miniaturized electronics.
Application domains for micro PCB/SMT span the most demanding sectors of electronics manufacturing: consumer wearables and smartphones; 5G mmWave RF modules; medical implants and diagnostic equipment; ADAS automotive radar and vision processors; high-performance computing accelerators; and aerospace/defense avionics. In every case, the driver is the same: maximum functionality per unit area while maintaining signal integrity, thermal reliability, and long-term product life.
How Micro PCB/SMT Technologies Work
Microvia HDI PCB Fabrication
Microvia PCB fabrication begins after standard inner-layer processing. Sequential build-up (SBU) lamination adds new dielectric and copper layers one pair at a time, each pair receiving its own laser-drilling and copper-plating cycle before the next lamination step. CO₂ or UV laser systems drill blind microvias with wall angles of 60–80°, creating a conical frustum profile that promotes complete electrolytic copper fill. Copper is plated at current densities of 20–30 ASF to form via wall thicknesses of 20–25 µm. After plating, vias are planarized using chemical-mechanical polishing (CMP) to maintain pad coplanarity within ±15 µm. The via fill factor is controlled to ≥95 %, eliminating internal voids that would otherwise reduce thermal conductivity and create stress concentration points during thermal cycling.
Micro-Component SMT Assembly
Micro-component placement requires a fundamentally different process window than standard 0402 or 0603 assembly. Pick-and-place machines for 01005 components require specialized vacuum nozzles (0.3–0.5 mm diameter), sub-30 µm @3σ placement accuracy, and machine-learning-enhanced vision systems for component recognition at magnifications where the part covers only a few hundred pixels. Solder paste for 01005 apertures uses Type 4 or Type 5 paste (particle size 20–38 µm or 15–25 µm respectively) with laser-cut or electroformed stencils featuring trapezoidal aperture profiles that improve paste release from stencil walls.
Post-reflow inspection cannot rely on 2D AOI alone. 3D AOI with multi-angle illumination detects tombstoning, skew, and missing 01005 parts. 3D automated X-ray inspection (AXI) at resolution below 5 µm is required for BGA void analysis, ball collapse, and hidden bridging, with void quantification per IPC-7095 (maximum 25 % per ball for Class 2). Statistical process control (SPC) with Cpk ≥1.33 for paste volume, placement offset, and reflow temperature provides the continuous quality data needed to sustain process capability on high-density mixed-technology boards.
Key Features and Advantages
| Feature | Description | Benefit |
| Ultra-High Routing Density | Microvias (<150 µm) and stacked via structures increase trace channels and I/O breakout per unit area | Enables routing of 0.25 mm pitch BGAs and 100+ I/O CSPs without increasing layer count |
| Superior Signal Integrity | Shorter interconnects reduce parasitic inductance and capacitance; copper-filled vias eliminate stubs | Critical for SERDES, DDR5, and 5G mmWave requiring controlled impedance ±5 Ω |
| VIPPO / Via-in-Pad Capability | Microvias filled and plated under BGA pads with ±10 µm surface planarity | Prevents solder wicking; enables reliable assembly of 0.4 mm and 0.3 mm pitch BGAs |
| Micro-Component Placement Accuracy | Sub-30 µm @3σ pick-and-place with vision alignment handles 01005 and 0.2 mm pitch BGAs | Supports wearable, medical implant, and 5G module form factors impossible with standard assembly |
| Multi-Layer Stacked Microvia | Sequential lamination builds 1+N+1, 2+N+2, or any-layer HDI stack-ups with stacked blind/buried vias | Vertical routing flexibility for complex SoC, FPGA, and AI accelerator package escape |
| Comprehensive Inspection Chain | 3D SPI, 3D AOI, AXI (<5 µm resolution), microsectioning, and electrical test per IPC-A-610/IPC-7095 | Ensures BGA joint quality, via fill, and micro-component placement all meet Class 2/3 standards |
Technical Specifications
PCB Fabrication Parameters
| Parameter | Specification / Range |
| Microvia diameter (laser-drilled) | ≤150 µm finished diameter; standard range 75–150 µm (3–6 mil) |
| Minimum mechanical via (PTH) | 0.15 mm (6 mil) finished diameter |
| Microvia aspect ratio (IPC-2226) | ≤1:1 (depth not to exceed diameter) |
| Via fill factor | ≥95 % (copper or resin fill, void-free per X-ray) |
| VIPPO surface planarity | ±10 µm after CMP planarization |
| Layer-to-layer registration | ±25 µm (sequential lamination) |
| Minimum trace / space (HDI) | 2.5 mil / 2.5 mil (0.063 mm / 0.063 mm) |
| PCB layer count | 4–40 layers standard; up to 100 layers for specialty designs |
| Board thickness range | 0.13–7.0 mm |
| Laser drilling system | CO₂ (large via, cost-effective) or UV (finer vias, better aspect ratio control) |
| Copper plating current density | 20–30 ASF for via barrel; wall thickness 20–25 µm |
| Surface finish options | ENIG, ENEPIG, Immersion Silver, OSP, Hard Gold |
| PCB certifications / Standards | IPC-A-600, IPC-6012, IPC-2226, IPC-4761, UL, ISO 9001, RoHS, REACH |
SMT Assembly Parameters
| Parameter | Specification / Range |
| Micro-component minimum size | 01005 (0.4×0.2 mm, ~0.04 mg) imperial; 008004 metric |
| BGA minimum pitch (assembly) | 0.2 mm (sub-0.3 mm requires stacked microvias + VIPPO) |
| SMT placement accuracy | ±30 µm @3σ (micro-BGA/01005); ±35 µm (standard fine-pitch) |
| Solder paste type (01005) | Type 4 (20–38 µm) or Type 5 (15–25 µm) particle size |
| Stencil type | Electroformed nickel (micro-components); laser-cut SS (standard); step stencil (mixed height) |
| Reflow peak temperature (SAC305) | 235–245°C; ramp rate <3°C/sec; time above liquidus 60–90 s |
| Reflow temperature uniformity | ±2°C across board to prevent tombstoning of 01005 components |
| Nitrogen atmosphere reflow | <500 ppm O₂; reduces oxidation-related defects by up to 30 % |
| SPC control targets | Cpk ≥1.33 for paste volume, placement offset, and reflow temperature |
| BGA void acceptance (IPC-7095) | ≤25 % void area per ball (Class 2); stricter for Class 3 |
| SMT certifications / Standards | IPC-A-610, IPC-7095, IPC-7093, J-STD-020, RoHS |
HDI Stack-Up and Assembly Design Options
Microvia PCB Stack-Up Configurations
1+N+1 HDI
One build-up layer each side of the core. Supports 0.5 mm BGA escape with via-in-pad. Lowest cost HDI entry point; 5–10 business day prototype lead time. Typical applications: IoT modules, entry-level wearables, USB-C controller boards.
2+N+2 HDI
Two sequential build-up layers each side; required for 0.4 mm pitch BGA with staggered microvias. Supports DDR4/DDR5 memory interfaces and mid-range SoC packages. Prototype lead time 10–15 days.
3+N+3 / Any-Layer HDI
Three or more build-up layers; stacked microvia columns connect any layer to any layer. Used for 0.25–0.3 mm pitch micro-BGAs in flagship smartphones, ADAS processors, and AI accelerator cards. Highest cost; longest lead time.
Via Types and Fill Options
- Blind microvia: Surface layer to adjacent inner layer; CO₂ or UV laser drilled. Standard HDI building block.
- Buried microvia: Inner-layer-to-inner-layer; formed before outer lamination cycles. Preserves surface routing space.
- Stacked microvia: Vertically aligned blind vias; requires Cu fill of lower via before upper drilling. Maximum density; used for ≤0.3 mm pitch breakout.
- Staggered microvia: Offset vias between adjacent layers; more mechanically robust than stacked; preferred for 0.4 mm pitch designs.
- VIPPO / IPC-4761 Type VII: Copper-filled via capped and plated over in component pad; mandatory for BGA ≤0.4 mm pitch.
- Fill material options: Electrolytic copper fill (best thermal conductivity), conductive epoxy (silver or carbon), or non-conductive resin + copper cap.
SMT Assembly Service Scope
- Component size range: 01005 passives through large connectors and power modules
- Package types handled: QFP, QFN, LGA, BGA, CSP, WLCSP, flip-chip, SiP, through-hole hybrid
- Mixed technology: SMT + PTH on same board; dual-side assembly with selective reflow
- Stencil options: Laser-cut SS (standard), electroformed Ni (micro-components), step stencil (mixed height components)
- Atmosphere: Air reflow (standard) or nitrogen (<500 ppm O₂) for 01005/fine-pitch BGA
- NPI/DFM support: Gerber + BOM review, IPC-2221 pad design verification, thermal profiling, first-article inspection (FAI)
Application Scenarios by Industry
Smartphones and Consumer Wearables
Modern flagship smartphones use any-layer HDI PCBs with stacked microvias to route hundreds of I/Os from 0.35 mm pitch application processor packages. Smartwatches and fitness trackers rely on 01005 passives placed between BGA pins and 2+N+2 build-up stack-ups to achieve sub-1 mm board thickness while integrating PMIC, RF, sensor, and memory packages on a single rigid-flex assembly.
5G Infrastructure and mmWave Modules
5G sub-6 GHz and mmWave RF front-end modules (FEMs) require HDI PCBs with controlled impedance (±5 Ω), low-loss dielectric materials (Rogers 4350B, Megtron 6), and micro-pitch flip-chip or WLCSP assembly with VIPPO pads. Antenna-in-Package (AiP) designs for 28 GHz and 39 GHz bands demand 2 mil/2 mil trace/space and placement accuracy below 15 µm for phased array element alignment.
Medical Implants and Diagnostic Equipment
Implantable cardiac devices, cochlear implants, and neural stimulators use 008004 and 01005 components on multi-layer rigid-flex PCBs to achieve the smallest possible implant volume. IPC-A-610 Class 3 assembly standards apply, with 100 % X-ray inspection of all BGA joints and stringent biocompatibility requirements for encapsulation materials. Diagnostic imaging equipment uses high-layer-count HDI PCBs for FPGA-based signal processing with controlled-impedance DDR4/DDR5 interfaces.
Automotive ADAS and EV Electronics
ADAS radar, camera, and LiDAR control units use automotive-grade HDI PCBs (AEC-Q200 components, −40°C to +125°C thermal cycling per IPC-TM-650 Method 2.6.7.2) with CTE-matched copper plating to prevent via fatigue. EV battery management systems (BMS) and on-board chargers integrate micro-pitch current sensing ICs in QFN packages demanding void-free solder joints per IPC-7093.
High-Performance Computing and AI Accelerators
Server motherboards, GPU boards, and AI accelerator cards use 2+N+2 or 3+N+3 HDI PCBs to route 1000+ ball HBM2e and GDDR6X memory packages with 0.65 mm and 0.5 mm pitch. PCIe Gen 5 (32 GT/s) and CXL 3.0 interfaces demand impedance-controlled microvia structures and back-drilling to eliminate via stubs that cause signal reflections at high data rates.
Aerospace and Defense Avionics
Avionics processors, guidance control systems, and satellite subsystems require HDI PCBs with strict tolerances for dielectric stability, Z-axis CTE, and blind via reliability across high-G shock and wide temperature ranges (−55°C to +125°C). IPC-6012 Class 3/A (space and military) specifications mandate enhanced copper plating thickness, X-ray and microsection quality verification, and full lot traceability.
Design and Procurement Guide
Prototype and NPI Services
- Prototype microvia PCBs: As few as 1–5 panels; 5–10 business days for 1+N+1 HDI; 10–15 days for 2+N+2 and beyond
- NPI engineering support: DFM review for HDI stack-up, VIPPO design verification, and BGA escape routing feasibility before tooling release
- First article inspection (FAI): 100 % microsection, X-ray, and electrical continuity on prototype lot before production release
Volume Production and Quality Systems
- Flexible MOQ: Many HDI PCB suppliers accept orders from 1–100 panels for prototypes, scaling to multi-thousand panel production with tiered pricing
- Lead time: Standard production 15–25 days; expedite options 7–10 days depending on layer count and via complexity
- In-process inspection: 3D SPI for paste volume, AOI after placement, real-time thermal profiling during reflow
- Final inspection: IPC-A-610 Class 2/3 visual + AOI, AXI for BGA, flying probe or ICT electrical test, microsection per IPC-TM-650 2.1.1
- Reliability testing: Thermal cycling (−40°C to +125°C), HAST, IST interconnect stress testing, cross-section analysis
Supplier Certification Requirements
| Certification / Standard | Scope | When to Require |
| IPC-A-600 Class 2/3 | Bare PCB acceptability criteria | All HDI PCB orders |
| IPC-6012 Class 2/3 (or 3/A) | PCB qualification and performance specification; 3/A for military/space | All HDI PCB orders; mandatory for defense/space |
| IPC-A-610 Class 2/3 | Assembled board acceptability criteria | All SMT assembly orders |
| IPC-7095 | BGA design and assembly process implementation; void acceptance criteria | Any BGA or micro-BGA assembly |
| IPC-2226 | HDI PCB design standard | Reference for design; confirm supplier familiarity |
| ISO 9001:2015 | Quality management system | All suppliers; baseline requirement |
| UL Recognition | North American safety compliance for PCB substrate | Products sold in North America |
| IATF 16949 | Automotive quality management; PPAP documentation | Any automotive program (AEC-Q200 component traceability) |
| ISO 13485 | Medical device quality management system | Any medical device assembly; FDA 21 CFR Part 820 alignment |
| RoHS / REACH | Restricted substances compliance; halogen-free laminates and Pb-free solder | All programs (mandatory for EU; best practice globally) |
Technology Comparison: Microvia HDI vs. Standard PCB vs. Standard SMT
| Attribute | Microvia HDI + Micro SMT | Standard Multilayer PCB | Standard SMT (0402+) |
| Minimum via diameter | 50–150 µm (laser-drilled) | 0.2–0.3 mm (mechanical drill) | N/A (board-level parameter) |
| Minimum component size | 01005 (0.4×0.2 mm) or 008004 | 0402 (1.0×0.5 mm) typical | 0402–0603 standard |
| Minimum BGA pitch | 0.2–0.3 mm (stacked VIPPO) | 0.8–1.0 mm (dog-bone fanout) | 0.8 mm (standard fan-out) |
| Routing density | Very high (2.5/2.5 mil) | Moderate (3.5/3.5 mil) | Low–moderate |
| Board layer count | 4–18+ (sequential lamination) | 4–16 (standard press) | Any |
| Assembly accuracy required | ±15–30 µm @3σ (micro-BGA/01005) | ±75–100 µm (standard SOP/QFP) | ±75–100 µm |
| Inspection requirement | 3D AXI mandatory + 3D SPI + 3D AOI | 2D AOI + spot X-ray | 2D AOI (standard) |
| Relative fabrication cost | High (sequential lamination, laser drill) | Low–moderate | Low–moderate |
| Typical application | Smartphones, medical implants, 5G, ADAS, HPC | Industrial controls, power supplies, IoT | Consumer electronics, general PCBs |
Frequently Asked Questions
What is the difference between a microvia and a standard blind via?
A microvia is defined by IPC-2226 as a laser-drilled via with a finished diameter at or below 150 µm (6 mil) and an aspect ratio (depth-to-diameter) of 1:1 or less. Standard blind vias — which may be laser or mechanically drilled — can have diameters from 0.15 mm to 0.3 mm and may span two or more layers. Microvias are restricted to connecting only adjacent layers to maintain the 1:1 aspect ratio necessary for reliable copper fill. In HDI designs, multiple stacked or staggered microvias achieve connections spanning several layers, each individual via remaining within the microvia aspect ratio specification.
When should I use stacked microvias versus staggered microvias?
Stacked microvias — where via centers on adjacent build-up layers are vertically aligned — provide the highest routing density and are the only viable option for 0.25 mm and 0.3 mm pitch BGA breakout using inverted pyramid escape patterns. However, stacked microvias require complete copper fill of the inner via before the outer via can be drilled above it, adding lamination cycles and cost, and they concentrate thermal stress at the stacked column — making CTE-matched plating critical for reliability. Staggered microvias — offset vias between adjacent layers — are mechanically more robust, less prone to fatigue cracking during thermal cycling, and easier to plate reliably, requiring slightly more routing space. Industry-standard guidance: use staggered microvias where design pitch permits (generally 0.4 mm BGA and above), and reserve stacked microvias for 0.25–0.3 mm pitch devices where routing space is genuinely insufficient.
What causes tombstoning in 0201 and 01005 components, and how is it prevented?
Tombstoning occurs when one end of a two-terminal passive lifts vertically during reflow. The root cause is asymmetric surface tension: if one solder joint melts and wets before the other, the molten solder’s surface tension exerts a rotational moment that stands the component upright. Contributing factors include pad asymmetry (unequal pad areas or different thermal mass), solder paste volume imbalance between the two pads, and thermal gradients across the board during the reflow soak zone. Prevention: non-solder mask defined (NSMD) pad designs with equal pad geometry; Type 4 or Type 5 solder paste with homogeneous printing verified by 3D SPI (target Cpk ≥1.33 for paste volume, CV <10 %); symmetric component orientation relative to PCB travel direction; and a controlled soak stage at 180–200°C to equalize board temperature before the reflow peak.
What inspection methods are mandatory for BGA and micro-BGA assemblies?
BGA and micro-BGA solder joints are hidden under the package body and cannot be reliably assessed by visual inspection or standard 2D AOI. The mandatory inspection chain for production assemblies is: 3D Solder Paste Inspection (3D SPI) before placement to verify paste volume and height at each BGA pad; 3D Automated Optical Inspection (3D AOI) after placement to confirm component alignment; and Automated X-ray Inspection (AXI or 3D AXI) after reflow to detect bridging, voiding, ball collapse, head-in-pillow (HiP), and missing balls. IPC-7095 defines acceptance criteria: for Class 2 assemblies, void area per ball must not exceed 25 %. For micro-BGA at 0.3 mm pitch and below, AXI resolution must be below 5 µm to distinguish adjacent balls. Periodic microsectioning of production panels validates plating thickness, via fill quality, and intermetallic compound formation.
What certifications should I require from a micro PCB/SMT service provider?
For a comprehensive micro PCB/SMT procurement qualification, require: IPC-A-600 Class 2 or 3 for bare PCB acceptability; IPC-6012 Class 2 or 3 (Class 3/A for military/space) for PCB qualification; IPC-A-610 Class 2 or 3 for assembled board acceptability; IPC-7095 for BGA process implementation; IPC-2226 for HDI PCB design; ISO 9001:2015 for quality management; UL recognition for North American safety compliance; and RoHS/REACH compliance documentation for halogen-free laminates and lead-free solder. Automotive programs, additionally require IATF 16949 certification and AEC-Q200 qualified component traceability. For medical devices, require ISO 13485 certification from the assembly provider and verification that their process has been qualified under FDA 21 CFR Part 820.
Conclusion
The choice of microvia HDI and micro-SMT technology is driven by component pitch, not preference. When your BGA pitch drops below 0.5 mm, standard dog-bone fanout runs out of space and you need microvias. The pitch reaches 0.4 mm, VIPPO becomes mandatory to prevent solder wicking. When your passive component is 0201 or smaller, you need Type 4/5 paste, electroformed stencils, and a placement machine calibrated to sub-30 µm accuracy. These are not premium options — they are the minimum process requirements at those geometries.
Find What You Need on LCSC
LCSC Electronics stocks a comprehensive range of components for high-density micro-SMT designs — including 0201 and 01005 chip resistors and MLCC capacitors, fine-pitch QFN and LGA ICs, micro-BGA memory and processors, WLCSP RF devices, and precision passive components in automotive-grade (AEC-Q200) and industrial-grade packages. Whether you are populating a 2+N+2 HDI smartphone board, sourcing 01005 decoupling capacitors for a BGA power rail, specifying AEC-Q200 MLCC components for an ADAS sensor PCB, or building a BOM for a medical device with ISO 13485 traceability requirements, LCSC’s parametric search lets you filter by package size, pitch, temperature rating, tolerance.
