Infineon S28HL01GTFPBHV030

The Cypress Semper Flash Octal family of products are high-speed CMOS, MirrorBit NOR flash devices that are compliant with the JEDEC JESD251 eXpanded SPI (xSPI) specification. Semper Flash is designed for Functional Safety with development according to ISO 26262 standard to achieve ASIL-B compliance and ASIL-D readiness. Semper Flash with Octal Interface devices support both the Octal Peripheral Interface (OPI) as well as Legacy x1 Serial Peripheral Interface (SPI). Both interfaces serially transfer transactions reducing the number of interface connection signals. SPI supports SDR whereas OPI supports both SDR and DDR. Read operations from the device are burst oriented. Read transactions can be configured to use either a wrapped or linear burst. Wrapped bursts read from a single page whereas linear bursts can read the whole memory array. The erased state of each memory bit is a logic 1. Programming changes a logic 1 (HIGH) to a logic 0 (LOW). Only an erase operation can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete sector (4 KBs or 256 KBs). Semper Flash provides a flexible sector architecture. The address space can be configured as either a uniform 256 KB sector array, or a hybrid configuration 1 where thirty-two 4 KB sectors are either grouped at the top or at the bottom while the remaining sectors are all 256 KB, or a hybrid configuration 2 where the thirty-two 4 KB sectors are equally split between the top and the bottom while the remaining sectors are all 256 KB. The Page Programming Buffer used during a single programming operation is configurable to either 256 bytes or 512 bytes. The 512 byte option provides the highest programming throughput. The Semper Flash with Octal Interface family consists of multiple densities with, 1.8V and 3.0V core and I/O voltage options. The device control logic is subdivided into two parallel operating sections: the Host Interface Controller (HIC) and the Embedded Algorithm Controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs as needed to complete read, program, and write data transfers with the host system. The HIC delivers data from the currently entered address map on read transfers; places write transfer address and data information into the EAC command memory, and notifies the EAC of power transition, and write transfers. The EAC interrogates the command memory, after a program or write transfer, for legal command sequences and pe

• Cypress 45-nm MirrorBit technology that stores two data bits in each memory array cell
• Sector Architecture options: Uniform: Address space consists of all 256 KB Sectors; Hybrid: Configuration 1 - Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom while the remaining sectors are all 256 KB; Configuration 2 - Address space consists of thirty-two 4 KB sectors equally split between top and bottom while the remaining sectors are all 256 KB
• Page Programming buffer of 256 or 512 bytes
• OTP Secure Silicon array of 1024 bytes (32x32 bytes)
• Octal Interface (8S-8S-8S, 8D-8D-8D): JEDEC eXpanded SPI (JESD251) compliant; SDR option runs up to 200 MBps (200 MHz clock speed); DDR option runs up to 400 MBps (200 MHz clock speed); Supports Data Strobe (DS) to simplify the read data capture in high-speed systems
• Serial Peripheral Interface (1S-1S-1S): JEDEC eXpanded SPI (JESD251) compliant; SDR option runs up to 21 MBps (166 MHz clock speed)
• Safety Features: Functional Safety with the Industry’s first ISO26262 ASIL B compliant and ASIL D ready NOR flash; EnduraFlex Architecture provides High-Endurance and Long Retention Partitions; Interface CRC detects errors on communication interface between host controller and Semper Flash device; Data Integrity CRC detects errors in memory array; SafeBoot reports device initialization failures, detects configuration corruption and provides recovery options; Built-in Error Correcting Code (ECC) corrects Single-bit Error and detects Double-bit Error (SECDED) on memory array data; Sector Erase Status indicator for power loss during erase; Legacy Block Protection for memory array and device configuration; Advanced Sector Protection for individual memory array sector based protection
• AutoBoot enables immediate access to the memory array following power-on
• Hardware Reset through CS# Signaling method (JEDEC) OR individual RESET# pin
• Serial Flash Discoverable Parameters (SFDP) describing device functions and features
• Device Identification, Manufacturer Identification and Unique Identification
• 256 Mb Devices: Min. 640,000 Program-Erase Cycles for the Main array
• 512 Mb Devices: Min. 1,280,000 Program-Erase Cycles for the Main array
• 1 Gb Devices: Min. 2,560,000 Program-Erase Cycles for the Main array
• All Devices: Min. 300,000 Program-Erase Cycles for the 4 KB Sectors; Minimum 25 Years Data Retention
• 1.7-V to 2.0-V (HS-T)
• 2.7-V to 3.6-V (HL-T)
• Industrial (-40 ℃ to +85 ℃)
• Industrial Plus (-40 ℃ to +105 ℃)
• Automotive AEC-Q100 Grade 3 (-40 ℃ to +85 ℃)
• Automotive AEC-Q100 Grade 2 (-40 ℃ to +105 ℃)
• Automotive AEC-Q100 Grade 1 (-40 ℃ to +125 ℃)