Rochester Electronics MD82C284-8/B
| Fabricante | |
| N.º de pieza fab. | MD82C284-8/B |
| Nº LCSC | C3607259 |
| Emb. | PLCC-20 |
| Número de Cliente | |
| Atrib. clave | 5V PLCC-20 Clock Generators, PLLs, Frequency Synthesizers |
| Hoja de Datos | Rochester Electronics MD82C284-8/B |
Especificaciones del Producto
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Fabricante | Rochester Electronics | |
| Emb. | PLCC-20 | |
| Operating Temperature | 0℃~+70℃ | |
| Clock/Oscillator | Built-in;External | |
| Voltage - Supply | 5V | |
| Output Frequency(Max) | - | |
| Interface | - | |
| Phase Offset | - | |
| Period Jitter, Peak-to-Peak | -;- | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | - |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Fabricante | Rochester Electronics | |
| Emb. | PLCC-20 | |
| Operating Temperature | 0℃~+70℃ | |
| Clock/Oscillator | Built-in;External | |
| Voltage - Supply | 5V | |
| Output Frequency(Max) | - | |
| Interface | - |
| Tipo | Descripción | |
|---|---|---|
| Phase Offset | - | |
| Period Jitter, Peak-to-Peak | -;- | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | - |
Descripción
The 82C284 generates clock, ready, and reset signals for the 80286 processor and its support components. It incorporates a crystal-controlled oscillator, clock generator, peripheral clock generator, multi-bus ready synchronization logic, and system reset generation logic. The CLK output provides fundamental timing for 80286 systems and can be driven by either an internal crystal oscillator or an external source. PCLK provides a clock for peripherals at half the CLK frequency with a 50% duty cycle. The oscillator is a linear Pierce oscillator requiring an external parallel-resonant, fundamental-mode crystal. Termination of CLK is recommended above 10MHz to prevent signal reflections and ringing. The reset logic asserts RESET (active high) when the RES input is asserted (active low).
Características
- High-speed CHMOS III technology
- Crystal or TTL signal frequency source
- Local ready and multi-bus ready synchronization
- System reset output generation
- Available in 18-pin Cerclip and 20-pin PLCC packages
Aplicaciones
- 80286 processor systems
- Support component systems
| Cant. | Prec. unit.(Solo como referencia) | Importo total |
|---|---|---|
| 1+ | $ 138.9238 | $ 138.92 |
| 200+ | $ 53.7614 | $ 10752.28 |
| 500+ | $ 51.8718 | $ 25935.90 |
| 1,000+ | $ 50.9386 | $ 50938.60 |
Encapsulado Estándar1/Full Bag | ||
Especificaciones del Producto
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Fabricante | Rochester Electronics | |
| Emb. | PLCC-20 | |
| Operating Temperature | 0℃~+70℃ | |
| Clock/Oscillator | Built-in;External | |
| Voltage - Supply | 5V | |
| Output Frequency(Max) | - | |
| Interface | - | |
| Phase Offset | - | |
| Period Jitter, Peak-to-Peak | -;- | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | - |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Fabricante | Rochester Electronics | |
| Emb. | PLCC-20 | |
| Operating Temperature | 0℃~+70℃ | |
| Clock/Oscillator | Built-in;External | |
| Voltage - Supply | 5V | |
| Output Frequency(Max) | - | |
| Interface | - |
| Tipo | Descripción | |
|---|---|---|
| Phase Offset | - | |
| Period Jitter, Peak-to-Peak | -;- | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | - |
Descripción
The 82C284 generates clock, ready, and reset signals for the 80286 processor and its support components. It incorporates a crystal-controlled oscillator, clock generator, peripheral clock generator, multi-bus ready synchronization logic, and system reset generation logic. The CLK output provides fundamental timing for 80286 systems and can be driven by either an internal crystal oscillator or an external source. PCLK provides a clock for peripherals at half the CLK frequency with a 50% duty cycle. The oscillator is a linear Pierce oscillator requiring an external parallel-resonant, fundamental-mode crystal. Termination of CLK is recommended above 10MHz to prevent signal reflections and ringing. The reset logic asserts RESET (active high) when the RES input is asserted (active low).
Características
- High-speed CHMOS III technology
- Crystal or TTL signal frequency source
- Local ready and multi-bus ready synchronization
- System reset output generation
- Available in 18-pin Cerclip and 20-pin PLCC packages
Aplicaciones
- 80286 processor systems
- Support component systems
Cumplimiento & Códigos de Exportación
| Tipo | Detalles |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Tipo | Detalles |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Tipo | Detalles |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |