NXP MCF51JE128VMB

The MCF51JE256 series devices are low-cost, low-power, high-performance ColdFire V1 32-bit microcontrollers (MCUs).

• Operating temperature range: -40℃ to 105℃; CPU frequency up to 50.33 MHz at voltages above 2.4V, up to 40 MHz above 2.1V, and up to 20 MHz above 1.8V
• ColdFire instruction set architecture version C (ISA_C)
• 32-bit multiply-accumulate (MAC) supporting signed/unsigned integer and signed fractional inputs
• 256 K Flash comprising two independent 128 K Flash arrays; read/program/erase supported across full operating voltage and temperature range; interrupt handling permitted during programming
• 32 KB system RAM
• Security circuitry to prevent unauthorized access to RAM and Flash contents
• Two ultra-low-power stop modes; unused module clocks can be disabled via peripheral clock enable registers to reduce current consumption
• Time of Day (TOD): 1/4-second ultra-low-power counter supporting timeouts up to 64 seconds
• Ultra-low-power external oscillator usable in stop mode, providing accurate clock source for TOD; typical wake-up time from stop3 mode: 6 µs
• Oscillator (XOSC1): loop-controlled Pierce oscillator; configured for 32.768 kHz crystal or ceramic resonator for TOD operation
• Oscillator (XOSC2): high-frequency crystal input, providing reference to MCG for system clock and USB operation
• Multipurpose Clock Generator (MCG) with integrated PLL and FLL; precise trimming of internal reference achieves 0.2% resolution, with typical deviation of +0.5% to -1% across full temperature and voltage range; CPU frequencies up to 50 MHz
• Watchdog normal operation (COP) reset; selectable operation using dedicated 1 kHz internal clock source or bus clock
• Low-voltage detect with reset or interrupt, selectable trip point; independent low-voltage warning with selectable interrupt and selectable trip point
• Illegal opcode and illegal address detection with reset
• Flash block protection per Flash array to prevent accidental write/erase
• Hardware CRC for fast cyclic redundancy check
• Integrated ColdFire DEBUG_Rev_B+ interface with single-wire BDM connection; same electrical interface as S08 series debug module
• Real-time debug with 6 hardware breakpoints (4 PC breakpoints, 1 address breakpoint, 1 data breakpoint)
• On-chip trace buffer with programmable start/stop recording conditions
• USB dual-role USB On-The-Go (OTG) device supporting host, device, or OTG configuration; on-chip transceiver and 3.3V regulator to reduce system cost; fully compliant with USB Specification 2.0; supports control, bulk, interrupt, and isochronous transfers
• Two SCIs (SCIx) with optional 13-bit break; SCI1 and SCI2 support connecting Rx input to PRACMP output; SCI1 and SCI2 Tx support high-current drive; Rx edge detection supports wake-up from stop3
• SPI1: serial peripheral interface with 32-bit FIFO buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shift
• SPI2: serial peripheral interface; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shift
• IIC: up to 100 kbps at maximum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode and 10-bit addressing
• CMT: carrier modulator timer for remote control communication, with carrier generator, modulator, and dedicated infrared output (IRO) driver; also usable as output compare timer
• Two 4-channel timer/PWM modules (TPMx); each channel selectable as input capture, output compare, or buffered edge-aligned/center-aligned PWM; external clock input/pulse accumulator supported
• Mini-FlexBus: multipurpose external bus interface with user-programmable chip selects; supports address and data line multiplexing options
• PRACMP: analog comparator with optional interrupt; selectable comparison against programmable internal reference voltage; operable in stop3 mode
• ADC12: 12-bit successive approximation ADC; up to 12 single-ended channels; internal bandgap reference channel; operable in stop3 mode; operational voltage range 1.8V to 3.6V
• PDB: programmable delay block with 16-bit counter, modulus, and prescaler; reference clock configurable from bus clock divided by 1 to 2048; 8 trigger outputs to ADC module for periodic coordination of ADC sampling sequences with sequence-complete interrupt; back-to-back mode and timed mode supported
• DAC: 12-bit resolution; configurable settling time
• Up to 68 GPIO and 1 output-only pin
• Voltage reference output (VREFO)
• Dedicated IRO pin with high-current sink capability
• Up to 16 KBI pins with selectable polarity
• Up to 16 rapid GPIO (RGPIO) pins