TI DM54LS298J/883

This device is a high-speed quad two-port register. Under the control of a common select input (S), it selects 4-bit data from two sources (ports). The selected data is synchronously transferred to the 4-bit output register on the high-to-low transition of the clock input (CP). The 4-bit output register is fully edge-triggered. To ensure predictable operation, the data inputs (I0x and I1x) and select input (S) need only be stable one setup time prior to the high-to-low clock transition.