ST STM32U385CGU6

The STM32U385xx devices belong to the ultra-low-power microcontroller family (STM32U3 series) based on the high-performance Arm Cortex-M33 32-bit RISC core. They operate at frequencies up to 96 MHz. The Cortex-M33 core features a single-precision FPU, supporting all Arm single-precision data-processing instructions and all data types. The Cortex-M33 core also implements a full set of DSP instructions and an MPU to enhance application security. The STM32U3 series is the first STM32 family based on near-threshold voltage technology, achieving a breakthrough improvement in battery life. Leveraging near-threshold technology, STM32U3 devices reduce active current consumption to 10μA/MHz, significantly extending battery life.

• Incorporates ST's most advanced proprietary technology
• Ultra-low power consumption
• Supply voltage range: 1.71 V to 3.6 V
• Operating temperature range: -40 °C to +105 °C
• VBAT mode: powers RTC and 32 × 32-bit backup registers
• Stop 3 mode with 8 KB SRAM: 1.6 μA
• Stop 3 mode with full SRAM: 2.2 μA
• Stop 2 mode with 8 KB SRAM: 3.8 μA
• Stop 2 mode with full SRAM: 4.5 μA
• Run mode at 3.3 V (While(1), SMPS buck converter mode): 9.5 μA/MHz
• Run mode at 3.3 V/48 MHz (CoreMark, SMPS buck converter mode): 13 μA/MHz
• Run mode at 3.3 V/96 MHz (CoreMark, SMPS buck converter mode): 16 μA/MHz
• BOR available in all modes except Shutdown
• Arm 32-bit Cortex-M33 CPU with TrustZone and FPU
• ART Accelerator: 8 KB instruction cache enabling zero-wait-state execution from Flash and external memory up to 96 MHz, with MPU, 144 DMIPS, and DSP instructions
• Power management: embedded LDO and SMPS buck converter with dynamic switching and voltage scaling
• Benchmark scores: 395.4 CoreMark (4.12 CoreMark/MHz), 500 ULPMark-CP, 117 ULPMark-CM, 202000 SecureMark-TLS
• Memory: 1 MB Flash with ECC, 2 banks for simultaneous read/write; 256 KB SRAM with 64 KB hardware parity; OCTOSPI external memory interface supporting SRAM, PSRAM, NOR, NAND, and FRAM
• Security and cryptography: Arm TrustZone with securable I/Os, memories, and peripherals; flexible lifecycle scheme with RDP and password-protected debug; root of trust based on unique boot entry and secure hidden protection area (HDP); secure firmware installation (SFI) from embedded root security services (RSS); secure data storage using hardware unique key (HUK); secure firmware upgrade; Trusted Firmware for Cortex-M (TF-M); two AES coprocessors, one with side-channel attack resistance (SAES); SCA-resistant public key accelerator; key hardware protection; authentication keys; HASH hardware accelerator; NIST SP800-90B compliant TRNG; 96-bit unique ID; 512-byte OTP; anti-tamper protection
• Clock management: 4 to 50 MHz crystal oscillator; 32.768 kHz crystal oscillator for RTC (LSE); internal 16 MHz factory-trimmed RC (±1%); internal low-power RC at 32 kHz or 250 Hz (±5%); 2 internal multi-speed oscillators, 3 MHz to 96 MHz; internal 48 MHz clock with clock recovery; precision MSI in PLL mode up to 96 MHz using 32.768 kHz, 16 MHz, or 32 MHz crystal oscillator
• GPIO: up to 82 fast I/Os with interrupt capability, mostly 5 V-tolerant, up to 14 I/Os independently powered down to 1.08 V
• Up to 15 timers and 2 watchdogs: 1 × 16-bit advanced motor control timer; 3 × 32-bit and 3 × 16-bit general-purpose timers; 2 × 16-bit basic timers; 4 × low-power 16-bit timers (available in Stop mode); 2 watchdogs; 2 SysTick timers; RTC with hardware calendar, alarms, and calibration
• Up to 19 communication peripherals: 1 × USB 2.0 full-speed controller; 1 × SAI; 3 × I2C FM+ (1 Mbit/s), SMBus/PMBus; 2 × I3C (SDR) with I2C FM+ mode support; 2 × USART and 2 × UART (SPI, ISO 7816, LIN, IrDA, modem), 1 × LPUART; 3 × SPI (6 SPI total, including 1 via OCTOSPI and 2 via USART); 1 × CAN FD controller; 1 × SDMMC interface; 1 × audio digital filter with sound activity detection
• 12-channel GPDMA controller, operational in Sleep and Stop modes (up to Stop 2)
• Up to 21 capacitive sensing channels supporting touch keys, linear, and rotary touch sensors
• Rich analog peripherals (independently powered): 2 × 12-bit 2.5 Msps ADC with hardware oversampling; 12-bit DAC module with 2 D/A converters, low-power sample-and-hold, autonomous operation in Stop 1 mode; 2 × op-amps with built-in PGA; 2 × ultra-low-power comparators
• CRC calculation unit
• Debug and development support: SWD, JTAG, ETM
• All packages ECOPACK2 compliant