TI JM38510/07601BEA

These bidirectional shift registers incorporate virtually all of the features a system designer could want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating mode control inputs, and a direct clear line. The register has four distinct operating modes: inhibit clock (no operation), shift right (in the direction from QA to QD), shift left (in the direction from QD to QA), and parallel (broadside) load. Synchronous parallel loading is accomplished by entering four bits of data and raising both mode control inputs S0 and S1 high. Data is loaded into the associated flip-flops and appears at the outputs following the positive transition of the clock input; serial data flow is inhibited during loading. When S0 is high and S1 is low, a shift-right operation is synchronously performed with the rising edge of the clock pulse, and serial data in this mode is entered through the shift-right data input port. When S0 is low and S1 is high, data is synchronously shifted left, with new data entered through the shift-left serial input port. When both mode control inputs are low, the shift register clock is inhibited. The mode controls for the SN54194/SN74194 should be changed only while the clock input is high.

• Parallel inputs and outputs
• Four operating modes: synchronous parallel load, shift right, shift left, no operation
• Positive edge-triggered clock
• Direct clear