NXP MPC8541VTAPF

The MPC8541E integrates a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8541E is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology.

• Embedded e500 Book E-compatible core
• High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
• Dual-issue superscalar, 7-stage pipeline design
• 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
• Lockable L1 caches—entire cache or on a per-line basis
• Separate locking for instructions and data
• Single-precision floating-point operations
• Memory management unit especially designed for embedded applications
• Enhanced hardware and software debug support
• Dynamic power management
• Performance monitor facility
• Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std 802.11i, iSCSI, and IKE processing
• Contains 4 Crypto-channels, a Controller, and a set of crypto Execution Units (EUs)
• Public Key Execution Unit (PKEU) supporting RSA and Diffie-Hellman, Programmable field size up to 2048-bits, Elliptic curve cryptography, F2m and F(p) modes, Programmable field size up to 511-bits
• Data Encryption Standard Execution Unit (DEU) – DES, 3DES Two key (K1, K2) or Three Key (K1, K2, K3) ECB and CBC modes for both DES and 3DES
• Advanced Encryption Standard Unit (AESU) Implements the Rinjdael symmetric key cipher Key lengths of 128, 192, and 256 bits. Two key ECB, CBC, CCM, and Counter modes
• ARC Four execution unit (AFEU) Implements a stream cipher compatible with the RC4 algorithm 40- to 128-bit programmable key
• Message Digest Execution Unit (MDEU) – SHA with 160-bit or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm
• Random Number Generator (RNG) 4 Crypto-channels, each supporting multi-command descriptor chains Static and/or dynamic assignment of crypto-execution units via an integrated controller Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
• High-performance RISC CPM
• Two full-duplex fast communications controllers (FCCs) that support the following protocol: – IEEE Std 802.3/Fast Ethernet (10/100)
• Serial peripheral interface (SPI) support for master or slave I²C bus controller
• General-purpose parallel ports—16 parallel I/O lines with interrupt capability
• 256 Kbytes of on-chip memory
• Can act as a 256-Kbyte level-2 cache
• Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
• Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
• Full ECC support on 64-bit boundary in both cache and SRAM modes
• SRAM operation supports relocation and is byte-accessible
• Cache mode supports instruction caching, data caching, or both
• External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing).
• Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
• Supports locking the entire cache or selected lines – Individual line locks set and cleared through Book E instructions or by externally mastered transactions
• Global locking and flash clearing done through writes to L2 configuration registers
• Instruction and data locks can be flash cleared separately
• Read and write buffering for internal bus accesses
• Address translation and mapping unit (ATMU)
• Eight local access windows define mapping within local 32-bit address space
• Inbound and outbound ATMUs map to larger external address spaces – Three inbound windows plus a configuration window on PCI – Four inbound windows – Four outbound windows plus default translation for PCI
• Programmable timing supporting first generation DDR SDRAM
• 64-bit data interface, up to MHz data rate
• Four banks of memory supported, each up to 1 Gbyte
• DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
• Full ECC support
• Page mode support (up to 16 simultaneous open pages) Contiguous or discontiguous memory mapping Sleep mode support for self refresh DDR SDRAM Supports auto refreshing On-the-fly power management using CKE signal Registered DIMM support
• Fast memory access via JTAG port
• 2.5-V SSTL2 compatible I/O
• Programmable interrupt controller (PIC)
• Programming model is compliant with the OpenPIC architecture

• networking
• telecommunications
• wireless infrastructure applications