Intel/Altera EPM1270T144C5N

The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18μm six-metal-layer flash process. The logic element (LE) density ranges from 240 to 2,210 (equivalent macrocells from 128 to 2,210), and the non-volatile storage capacity is 8 Kbits. Compared with other CPLD architectures, MAX II devices offer a high number of I/Os, fast performance, and reliable adaptability. MAX II devices feature a MultiVolt core, user flash memory (UFM) blocks, and enhanced in-system programmability (ISP). They are designed to reduce cost and power consumption while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR), timing control, and device configuration control.

• Low-cost, low-power CPLD
• Instant-on, non-volatile architecture
• Standby current as low as 2 mA
• Fast propagation delay and clock-to-output times
• Four global clocks with two available clocks per LAB
• UFM block up to 8 Kbits for non-volatile storage
• MultiVolt core supports 3.3 V/2.5 V or 1.8 V external supply voltage
• MultiVolt I/O interface supports 3.3 V, 2.5 V, 1.8 V, and 1.5 V logic levels
• Bus-friendly architecture with programmable slew rate, drive strength, bus hold, and programmable pull-up resistors
• Schmitt trigger for noise-tolerant inputs (programmable per pin)
• Fully compliant with PCI SIG PCI Local Bus Specification Revision 2.2 for 3.3 V operation at 66 MHz
• Hot-plugging support
• Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990
• ISP circuitry compliant with IEEE Std. 1532

• Bus bridging
• I/O expansion
• Power-on reset (POR) and sequencing control
• Device configuration control