TI JM38510/34102BEA

Package options include plastic small-outline, ceramic chip carrier, and standard plastic and ceramic 300-mil DIP packages. The device contains two independent J-K positive-edge-triggered flip-flops. A low level on the preset (PRE) or clear (CLR) input sets or resets the output regardless of other input levels. When PRE and CLR are inactive (high), data on the J and K inputs meeting setup time requirements is transferred to the outputs on the rising edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval, data on the J and K inputs may change without affecting output levels. These versatile flip-flops can be used as toggle flip-flops by grounding K and tying J high, or as D-type flip-flops when J and K are connected together. The SN74F109 operates over a temperature range of 0°C to 70°C.