Infineon/CYPRESS MB9BF416RPMC-G-JNE2

The MB9B410R series are highly integrated 32-bit microcontrollers designed for embedded control applications requiring high performance and cost efficiency. Based on the Arm Cortex-M3 processor, this series integrates on-chip Flash and SRAM, along with peripheral functions including motor control timers, ADC, and communication interfaces. The products described in this datasheet belong to the TYPE4 product category in the FM3 Family Peripheral Manual.

• 32-bit Arm Cortex-M3 core, processor revision r2p1, operating frequency up to 144MHz
• Integrated MPU for enhanced embedded system reliability
• Integrated NVIC supporting 1 NMI and 48 peripheral interrupts with 16 priority levels
• Integrated 24-bit system timer for OS task management
• On-chip memory: Dual independent on-chip flash; main flash up to 512KB with built-in flash accelerator system featuring 16KB trace buffer; work flash 32KB; on-chip SRAM up to 64KB total, comprising two independent SRAM banks
• External bus interface: Supports SRAM, NOR and NAND flash devices; up to 8 chip selects; 8-bit/16-bit data width; up to 25-bit address; maximum area size 256MB; address/data multiplexing; external ready input support
• CAN interface: Up to 2 channels; CAN specification 2.0A/B compliant; max transfer rate 1Mbps; 32 message buffers
• Multi-function serial interface: Up to 8 channels, 4 of which feature 16-level × 9-bit FIFO buffers; operating modes: UART, CSIO, LIN, or I²C
• UART mode: Full-duplex double-buffered; parity selection (with/without); dedicated baud rate generator; external clock as serial clock; hardware flow control; multiple error detection functions
• CSIO mode: Full-duplex double-buffered; dedicated baud rate generator; overrun error detection
• LIN mode: LIN protocol Rev.2.1; full-duplex double-buffered; master/slave mode; LIN break field generation; LIN break delimiter generation; multiple error detection functions
• I²C mode: Standard mode and fast mode support
• DMA controller: 8 channels; independent bus from CPU; software or built-in peripheral request-initiated transfer; 32-bit transfer address space; block, burst, and demand transfer modes; byte, half-word, and word data transfer types
• ADC: Up to 16 channels; 12-bit resolution; successive approximation register type; 3 built-in units; conversion time 1.0μs @ 5V; priority conversion; scan conversion mode; built-in FIFO for conversion data storage
• Base timers: Up to 8 channels; selectable operating modes: 16-bit PWM timer, 16-bit programmable pulse generator timer, 16-bit/32-bit reload timer, or 16-bit/32-bit programmable waveform control timer
• GPIO: Pins not used for external bus or peripherals are available as GPIO with port relocation function