Intel/Altera EP1K100FC256-1

Altera ACEX 1K devices provide a high-utilization, low-cost architecture by combining a look-up table (LUT) architecture with embedded array blocks (EABs). LUT-based logic delivers optimized performance and efficiency for datapath, register-intensive, arithmetic, or DSP designs, while EABs implement RAM, ROM, dual-port RAM, or FIFO functions. These elements make the ACEX 1K suitable for complex logic and memory functions — such as DSP, wide datapath processing, data conversion, and microcontrollers — as required in high-performance communications applications. Based on reconfigurable CMOS SRAM elements, the ACEX 1K architecture incorporates all the features needed to implement common gate array macrofunctions, along with high pin counts for efficient interfacing with system components. Advanced process technology and low-voltage 2.5V core requirements enable ACEX 1K devices to address low-cost, high-volume applications ranging from DSL modems to low-cost switches. The ability to reconfigure ACEX 1K devices enables complete testing prior to shipment and allows designers to focus on simulation and design verification. The reconfigurability of ACEX 1K devices eliminates the inventory management associated with gate array designs and the need to generate test vectors for fault coverage.

• Programmable logic device (PLD) enabling low-cost SOPC integration in a single device
• Enhanced embedded array for macrofunctions such as efficient memory and dedicated logic functions
• Dual-port capability up to 16 bits wide per embedded array block (EAB)
• Logic array for general-purpose logic functions
• High density with typical gate counts of 10,000 to 100,000 (see Table 1)
• Up to 49,152 RAM bits (4,096 bits per EAB, all usable without reducing logic capacity)
• Cost-effective programmable architecture for high-volume applications
• Cost-optimized process
• Low-cost solution for high-performance communication applications
• System-level features
• MultiVolt™ I/O pins drivable by or capable of driving 2.5V, 3.3V, or 5.0V devices
• Low power consumption
• Bidirectional I/O performance (tSU and tCO) up to 250 MHz
• Full compliance with PCI SIG PCI Local Bus Specification Revision 2.2 for 3.3V operation at 33 MHz or 66 MHz
• Extended temperature range
• -1 speed grade devices compliant with PCI Local Bus Specification Revision 2.2 for 5.0V operation
• Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990, consuming no additional device logic
• 2.5V internal supply voltage operation
• In-circuit reconfiguration (ICR) via external configuration device, intelligent controller, or JTAG port
• ClockLock™ and ClockBoost™ options for reduced clock delay, clock skew, and clock multiplication
• Built-in low-skew clock distribution tree
• 100% functional testing of all devices; no test vectors or scan chains required
• I/O pin pull-up before and after configuration
• Flexible interconnect
• FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays
• Dedicated carry chain for arithmetic functions such as fast adders, counters, and comparators (used automatically by software tools and macrofunctions)
• Dedicated cascade chain for high-speed, high-fan-in logic functions (used automatically by software tools and macrofunctions)
• Tri-state emulation for internal tri-state buses
• Up to six global clock signals and four global clear signals
• Independent tri-state output enable control per pin
• Open-drain option per I/O pin
• Programmable output slew-rate control to reduce switching noise
• Pin-by-pin clamp-to-VCCIO selection
• Hot-socketing support
• Software design support and automatic place-and-route by Altera development system for Windows-based PCs, Sun SPARC workstations, and HP 9000 Series 700/800 workstations
• Flexible package options from 100 to 484 pins, including innovative FineLine BGA packages (see Tables 2 and 3)
• Additional design entry and simulation support via EDIF 200 and 300 netlist files, LPM, DesignWare components, Verilog HDL, VHDL, and interfaces to popular EDA tools from Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic