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Modelli EDAEasyEDA
AMD/XILINX XC95288XL-7FGG256C
| Produttore | |
| Cod. Prod. | XC95288XL-7FGG256C |
| Cod. LCSC | C1556328 |
| Imballo | FBGA-256 |
| Numero Cliente | |
| Attr. chiave | FBGA-256 FPGAs (Field Programmable Gate Array) RoHS |
| Scheda Tecnica | AMD/XILINX XC95288XL-7FGG256C |
Specifiche del Prodotto
Tutto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX | |
| Imballo | FBGA-256 |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX |
| Tipo | Descrizione | |
|---|---|---|
| Imballo | FBGA-256 |
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Descrizione
Traduzione AI
The XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 6 ns.
Caratteristiche
Traduzione AI
- 6 ns pin-to-pin logic delays
- System frequency up to 208 MHz
- 288 macrocells with 6,400 usable gates
- Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages
- Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
- Fast FLASH technology
- Advanced system features
- In-system programmable
- Superior pin-locking and routability with Fast CONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin with local inversion
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
- Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package
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| Qtà | Pr. unit.(Solo per riferimento) | Importo totale |
|---|---|---|
| 1+ | $ 44.932 | $ 44.93 |
| 200+ | $ 17.3878 | $ 3477.56 |
| 500+ | $ 16.7774 | $ 8388.70 |
| 1,000+ | $ 16.4761 | $ 16476.10 |
Package Standard90/Full Tray | ||
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Specifiche del Prodotto
Tutto
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX | |
| Imballo | FBGA-256 |
| Tipo | Descrizione | |
|---|---|---|
| Categoria | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Produttore | AMD/XILINX |
| Tipo | Descrizione | |
|---|---|---|
| Imballo | FBGA-256 |
Aiuto & FeedbackMostra prodotti simili (0) >
Descrizione
Traduzione AI
The XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 6 ns.
Caratteristiche
Traduzione AI
- 6 ns pin-to-pin logic delays
- System frequency up to 208 MHz
- 288 macrocells with 6,400 usable gates
- Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages
- Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
- Fast FLASH technology
- Advanced system features
- In-system programmable
- Superior pin-locking and routability with Fast CONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin with local inversion
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
- Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package
C1556328 Libreria EasyEDA
Conformità & Codici di Esportazione
| Tipo | Dettagli |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Tipo | Dettagli |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Tipo | Dettagli |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |