MICROCHIP AT91SAM9G46B-CU

The Atmel | SMART ARM926EJ-S-based SAM9G46 embedded microprocessor unit (eMPU) features the frequently requested combination of user interface functionality and high data rate connectivity, including LCD controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400 MHz and multiple 100+ Mbps data rate peripherals, the SAM9G46 provides adequate performance and bandwidth to the network or local storage media. The SAM9G46 eMPU supports DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 39 DMA channels, a dual external bus interface and distributed memory including a 64-Kbyte SRAM that can be configured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor and the high speed peripherals. On-chip hardware accelerators with DMA support enable high-speed data encryption and authentication of the transferred data or application. Supported standards are up to 256-bit AES, FIPS PUB 46-3 compliant TDES and FIPS Publication 180-2 compliant SHA1 and SHA256. A True Random Number Generator is embedded for key generation and exchange protocols. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports 0.8 mm ball pitch package for low cost PCB manufacturing. The SAM9G46 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes.

• 400 MHz ARM926EJ-S ARM Thumb Processor 32 Kbytes Data Cache, 32 Kbytes Instruction Cache, MMU
• 4-port, 4-bank DDR2/LPDDR Controller
• External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, SLC NAND Flash with ECC
• 64 Kbytes internal SRAM, single-cycle access at system speed or processor speed through TCM interface
• 64 Kbytes internal ROM, embedding bootstrap routine
• LCD Controller (LCDC) supporting STN and TFT displays up to 1280*860
• ITU-R BT. 601/656 Image Sensor Interface (ISI)
• Dual High Speed USB Host and a High Speed USB Device with On-Chip Transceivers
• 10/100 Mbps Ethernet MAC Controller (EMAC)
• Two High Speed Memory Card Hosts (SDIO, SDCard, e.MMC and CE ATA)
• AC’97 Controller (AC97C)
• Two Master/Slave Serial Peripheral Interfaces (SPI)
• 2 Three-channel 16-bit Timer/Counters (TC)
• Two Synchronous Serial Controllers (I2S mode)
• Four-channel 16-bit PWM Controller
• 2 Two-wire Interfaces (TWI)
• Four USARTs with ISO7816, IrDA, Manchester and SPI modes; one Debug Unit (DBGU)
• 8-channel 10-bit ADC with 4-wire Touchscreen support
• Write Protected Registers
• True Random Number Generator (TRNG)
• AES256-, 192-, 128-bit Key Algorithm
• TDES Compliant with FIPS PUB 46-3 Specifications
• SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2
• 133 MHz twelve 32-bit layer AHB Bus Matrix
• 39 DMA Channels
• Boot from NAND Flash, SDCard, DataFlash or serial DataFlash
• Reset Controller (RSTC) with on-chip Power-on Reset
• Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators
• Internal Low-power 32 kHz RC Oscillator
• One PLL for the system and one 480 MHz PLL optimized for USB High Speed
• Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
• Periodic Interval Timer (PIT), Watchdog Timer (WDT), Real-time Timer (RTT) and Real-time Clock (RTC)
• Five 32-bit Parallel Input/Output Controllers 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input
• 324-ball TFBGA - 15 x 15 x 1.2 mm, 0.8 mm pitch