Alliance Memory AS7C31024B-15TJCN
| 제조업체 | |
| 제조사 품번 | AS7C31024B-15TJCN |
| LCSC 번호 | C1351447 |
| 포장 | SOJ-32 |
| 고객 번호 | |
| 주요 제원 | 1Mbit Parallel Port (Parallel) SOJ-32 Memory RoHS |
| 데이터시트 | Alliance Memory AS7C31024B-15TJCN |
| 대체 부품 | 20 |
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Memory/Memory | |
| 제조업체 | Alliance Memory | |
| 포장 | SOJ-32 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function | |
| Memory Size | 1Mbit | |
| Voltage - Supply | 3V~3.6V;60mA | |
| Access Time | 15ns | |
| Standby Supply Current | 5mA | |
| Interface | Parallel Port (Parallel) |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Memory/Memory | |
| 제조업체 | Alliance Memory | |
| 포장 | SOJ-32 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function |
| 타입 | 설명 | |
|---|---|---|
| Memory Size | 1Mbit | |
| Voltage - Supply | 3V~3.6V;60mA | |
| Access Time | 15ns | |
| Standby Supply Current | 5mA | |
| Interface | Parallel Port (Parallel) |
개요
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (ΔI_AA, t_RC, Δt_WC) of 10/12/15/20 ns with output enable access times (Δ[t_OE]) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume I_SB power. If the bus is static, then full standby power is reached (I_SB1). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
주요 특징
- Industrial and commercial temperatures
- Organization: 131,072 words x8 bits
- High speed - 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
- Low power consumption: ACTIVE - 252 mW / max @ 10 ns
- Low power consumption: STANDBY - 18 mW / max CMOS
- 6T 0.18u CMOS technology
- Easy memory expansion with CE1, CE2, OE inputs
- TTL/LVTTL-compatible, three-state I/O
- 32-pin JEDEC standard packages
- 300 mil SOJ - 400 mil SOJ - 8x20mm TSOP 1
- 8x13.4mm sTSOP 1
- ESD protection ≥2000 volts
- Latch-up current ≥200 mA
| 수량 | 단가(참고용) | 총액 |
|---|---|---|
| 1+ | $ 3.3525 | $ 3.35 |
| 200+ | $ 1.2981 | $ 259.62 |
| 500+ | $ 1.2518 | $ 625.90 |
| 1,000+ | $ 1.2302 | $ 1230.20 |
표준 패키지22/Full Tube | ||
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Memory/Memory | |
| 제조업체 | Alliance Memory | |
| 포장 | SOJ-32 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function | |
| Memory Size | 1Mbit | |
| Voltage - Supply | 3V~3.6V;60mA | |
| Access Time | 15ns | |
| Standby Supply Current | 5mA | |
| Interface | Parallel Port (Parallel) |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Memory/Memory | |
| 제조업체 | Alliance Memory | |
| 포장 | SOJ-32 | |
| Operating Temperature | 0℃~+70℃ | |
| Features | Auto power-down function |
| 타입 | 설명 | |
|---|---|---|
| Memory Size | 1Mbit | |
| Voltage - Supply | 3V~3.6V;60mA | |
| Access Time | 15ns | |
| Standby Supply Current | 5mA | |
| Interface | Parallel Port (Parallel) |
개요
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (ΔI_AA, t_RC, Δt_WC) of 10/12/15/20 ns with output enable access times (Δ[t_OE]) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume I_SB power. If the bus is static, then full standby power is reached (I_SB1). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
주요 특징
- Industrial and commercial temperatures
- Organization: 131,072 words x8 bits
- High speed - 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
- Low power consumption: ACTIVE - 252 mW / max @ 10 ns
- Low power consumption: STANDBY - 18 mW / max CMOS
- 6T 0.18u CMOS technology
- Easy memory expansion with CE1, CE2, OE inputs
- TTL/LVTTL-compatible, three-state I/O
- 32-pin JEDEC standard packages
- 300 mil SOJ - 400 mil SOJ - 8x20mm TSOP 1
- 8x13.4mm sTSOP 1
- ESD protection ≥2000 volts
- Latch-up current ≥200 mA
C1351447 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| 타입 | 세부사항 |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
대체 부품
| MPN | 제조사 | 포장 | 재고 현황 | 단가 | ||
|---|---|---|---|---|---|---|
| AS7C31024B-15JCN | Alliance Memory | SOJ-32 | 0 | $ 3.3525 | ||
| AS7C31024B-15JCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.1844 | ||
| AS7C31024B-15TJCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.1844 | ||
| AS7C31025B-15JCN | Alliance Memory | SOJ-32 | 0 | $ 3.3525 | ||
| AS7C31025B-15TJCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.1844 | ||
| AS7C31025B-15JCNTR | Alliance Memory | SOJ-32 | 0 | $ 7.2371 | ||
| AS7C31025B-15TJCN | Alliance Memory | SOJ-32 | 0 | $ 7.6763 | ||
| CY7C109V33-15VC | Infineon/CYPRESS | BSOJ-32 | 0 | $ 0.1861 | ||
| CY7C1019BV33-15VC | Infineon/CYPRESS | BSOJ-32 | 0 | $ 0.2092 | ||
| CY7C1018BV33-15VI | Infineon/CYPRESS | BSOJ-32 | 0 | $ 0.1333 | ||
| CY7C1018CV33-15VXC | Infineon/CYPRESS | BSOJ-32 | 0 | $ 0.2432 | ||
| AS7C31024B-12JCN | Alliance Memory | SOJ-32 | 0 | $ 2.7659 | ||
| AS7C31024B-12TJCN | Alliance Memory | SOJ-32 | 0 | $ 3.3525 | ||
| AS7C31025B-12JCN | Alliance Memory | SOJ-32 | 0 | $ 3.3525 | ||
| AS7C31024B-20JCN | Alliance Memory | SOJ-32 | 0 | $ 3.8309 | ||
| AS7C31024B-20TJCN | Alliance Memory | SOJ-32 | 0 | $ 3.8309 | ||
| AS7C31025B-12TJCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.1844 | ||
| AS7C31024B-12TJCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.1844 | ||
| AS7C31024B-20JCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.6258 | ||
| AS7C31024B-20TJCNTR | Alliance Memory | SOJ-32 | 0 | $ 3.6258 |

