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Alliance Memory AS7C31024B-15TJCN product image
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Alliance Memory AS7C31024B-15TJCN

제조업체
제조사 품번
AS7C31024B-15TJCN
LCSC 번호
C1351447
포장
SOJ-32
고객 번호
주요 제원
1Mbit Parallel Port (Parallel) SOJ-32 Memory RoHS
데이터시트Alliance Memory AS7C31024B-15TJCN
대체 부품20
모든 주문 보장
100% 정품 · 30일 반품 또는 교환
품절
재입고 알림
최소값: 1배수: 1판매 단위: Piece
BOM 목록에 추가
수량단가(참고용)총액
1+$ 3.3525$ 3.35
200+$ 1.2981$ 259.62
500+$ 1.2518$ 625.90
1,000+$ 1.2302$ 1230.20
표준 패키지22/Full Tube
수량이 많을수록 더 좋은 가격?
$

제품 사양

전체
타입설명
카테고리Integrated Circuits (ICs)/Memory/Memory
제조업체Alliance Memory
포장SOJ-32
Operating Temperature0℃~+70℃
FeaturesAuto power-down function
Memory Size1Mbit
Voltage - Supply3V~3.6V;60mA
Access Time15ns
Standby Supply Current5mA
InterfaceParallel Port (Parallel)
도움말 및 피드백유사 제품 보기 (0) >

개요

AI 번역

The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (ΔI_AA, t_RC, Δt_WC) of 10/12/15/20 ns with output enable access times (Δ[t_OE]) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume I_SB power. If the bus is static, then full standby power is reached (I_SB1). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

주요 특징

AI 번역
  • Industrial and commercial temperatures
  • Organization: 131,072 words x8 bits
  • High speed - 10/12/15/20 ns address access time
  • 5, 6, 7, 8 ns output enable access time
  • Low power consumption: ACTIVE - 252 mW / max @ 10 ns
  • Low power consumption: STANDBY - 18 mW / max CMOS
  • 6T 0.18u CMOS technology
  • Easy memory expansion with CE1, CE2, OE inputs
  • TTL/LVTTL-compatible, three-state I/O
  • 32-pin JEDEC standard packages
  • 300 mil SOJ - 400 mil SOJ - 8x20mm TSOP 1
  • 8x13.4mm sTSOP 1
  • ESD protection ≥2000 volts
  • Latch-up current ≥200 mA

대체 부품

MPN제조사포장재고 현황단가
AS7C31024B-15JCNAlliance MemorySOJ-320$ 3.3525
AS7C31024B-15JCNTRAlliance MemorySOJ-320$ 3.1844
AS7C31024B-15TJCNTRAlliance MemorySOJ-320$ 3.1844
AS7C31025B-15JCNAlliance MemorySOJ-320$ 3.3525
AS7C31025B-15TJCNTRAlliance MemorySOJ-320$ 3.1844
AS7C31025B-15JCNTRAlliance MemorySOJ-320$ 7.2371
AS7C31025B-15TJCNAlliance MemorySOJ-320$ 7.6763
CY7C109V33-15VCInfineon/CYPRESSBSOJ-320$ 0.1861
CY7C1019BV33-15VCInfineon/CYPRESSBSOJ-320$ 0.2092
CY7C1018BV33-15VIInfineon/CYPRESSBSOJ-320$ 0.1333
CY7C1018CV33-15VXCInfineon/CYPRESSBSOJ-320$ 0.2432
AS7C31024B-12JCNAlliance MemorySOJ-320$ 2.7659
AS7C31024B-12TJCNAlliance MemorySOJ-320$ 3.3525
AS7C31025B-12JCNAlliance MemorySOJ-320$ 3.3525
AS7C31024B-20JCNAlliance MemorySOJ-320$ 3.8309
AS7C31024B-20TJCNAlliance MemorySOJ-320$ 3.8309
AS7C31025B-12TJCNTRAlliance MemorySOJ-320$ 3.1844
AS7C31024B-12TJCNTRAlliance MemorySOJ-320$ 3.1844
AS7C31024B-20JCNTRAlliance MemorySOJ-320$ 3.6258
AS7C31024B-20TJCNTRAlliance MemorySOJ-320$ 3.6258