ST STM32H730VBT6

32-bit Arm Cortex-M7 550 MHz microcontroller with 128 KB Flash, 564 KB RAM, 35 communication peripherals and analog interfaces, and hardware cryptography/hash functionality.

• Core：32-bit Arm Cortex-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories：128 Kbytes of embedded Flash memory with ECC; SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical real-time data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes); Flexible external memory controller with up to 24-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories; 2 x Octo-SPI interface with XiP and on-the-fly decryption support; 2 x SD/SDIO/MMC interface; Bootloader with security services support (SFI and SB-SFU)
• Graphics：Chrom-ART Accelerator graphical hardware accelerator enabling enhanced graphical user interface to reduce CPU load; LCD-TFT controller supporting up to XGA resolution
• Clock, reset and supply management：1.62 V to 3.6 V application supply and I/O; POR, PDR, PVD and BOR; Dedicated USB power; Embedded DCDC and LDO regulator; Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI; External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
• Low power：Sleep, Stop and Standby modes; VBAT supply for RTC, 32x32-bit backup registers
• Analog：2x16-bit ADC, up to 3.6 MSPS in 16-bit: up to 22 channels and 7.2 MSPS in double-interleaved mode; 1x12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels; 2x comparators; 2x operational amplifier GBW = 8 MHz; 2 x 12-bit D/A converters
• Digital filters for sigma delta modulator (DFSDM)：8 channels/4 filters
• 4 DMA controllers to offload the CPU：1 x MDMA with linked list support; 2 x dual-port DMAs with FIFO; 1 x basic DMA with request router capabilities
• 24 timers：Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input; 2x watchdogs, 1x SysTick timer
• Debug mode：SWD and JTAG interfaces; 2-Kbyte embedded trace buffer
• Up to 128 I/O ports with interrupt capability
• Up to 35 communication interfaces：Up to 5 x I2C FM+ interfaces (SMBus/PMBus); Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART; Up to 6 SPIs with 4 with mixed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode); 2x SAI (serial audio interface); 1 x FD/TT-CAN and 2xFD-CAN; 8- to 14-bit camera interface; 16-bit parallel slave synchronous interface; SPDIF-IN interface; HDMI-CEC; Ethernet MAC interface with DMA controller; USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY; SWPMI single-wire protocol master I/F; MDIO slave interface
• Mathematical acceleration：CORDIC for trigonometric functions acceleration; FMAC: Filter mathematical accelerator
• Digital temperature sensor
• Cryptographic/HASH acceleration：AES 128, 192, 256, TDES, HASH (MD5, SHA-1, SHA-2), HMAC; 2x OTFDEC AES-128 in CTR mode for OctoSPI memory encryption/decryption
• True random number generator
• CRC calculation unit
• RTC with sub-second accuracy and hardware calendar
• ROP, PC-ROP, tamper detection, secure firmware upgrade support
• 96-bit unique ID
• All packages are ECOPACK2 compliant