Infineon CY9BF522LPMC1-GNE2

This series consists of highly integrated 32-bit microcontrollers designed for embedded control applications, featuring low-power modes and competitive cost. Based on the Arm® Cortex®-M3 processor, these series integrate on-chip Flash and SRAM, along with a rich set of peripheral functions including various timers, ADC, DAC, and communication interfaces (USB, CAN, UART, CSIO, I2C, LIN).

• 32-bit Arm® Cortex®-M3 core, processor revision r2p1, operating frequency up to 72 MHz
• Integrated nested vector interrupt controller: 1 non-maskable interrupt and 48 peripheral interrupts, 16 priority levels
• 24-bit system timer for OS task management
• Dual-operation flash supporting simultaneous erase, write, and read operations on upper and lower banks; main area up to 256 Kbytes, work area 32 Kbytes, 0 wait-cycle read access
• Code protection security feature
• On-chip SRAM consisting of two independent banks, SRAM0 and SRAM1, each up to 16 Kbytes
• USB interface with device and host functionality, built-in USB PLL, USB 2.0 full-speed support
• USB device supports up to 6 endpoints: endpoint 0 for control transfers; endpoints 1 and 2 selectable for bulk, interrupt, or isochronous transfers; endpoints 3 to 5 selectable for bulk or interrupt transfers; endpoints 1 to 5 with double-buffer architecture
• USB host supports USB 2.0 full-speed/low-speed, bulk/interrupt/isochronous transfers, automatic device connect/disconnect detection, automatic IN/OUT token handshake packet handling, maximum 256-byte packet length, and wakeup function
• CAN interface compliant with CAN specification 2.0A/B, maximum transfer rate 1 Mbps, 32 built-in message buffers
• Multi-function serial interface up to 8 channels: 4 channels with 16-stage × 9-bit FIFO, 4 channels without FIFO
• Each channel selectable for UART, CSIO, or LIN operating mode
• UART: full-duplex double-buffered, selectable parity, dedicated baud rate generator, external clock as serial clock option, hardware flow control support
• CSIO: full-duplex double-buffered, dedicated baud rate generator, overrun error detection
• LIN: compliant with LIN protocol Rev.2.1, full-duplex double-buffered, master/slave mode, LIN break field and delimiter generation
• I2C supports standard mode and fast mode
• DMA controller with 8 independent channels, bus independent of CPU, software or built-in peripheral request-initiated transfers, 32-bit transfer address range, block/burst/demand transfer modes
• ADC up to 26 channels, 12-bit successive approximation type, 2 built-in units, conversion time 0.8 μs @ 5V, priority conversion and scan conversion modes, built-in FIFO for conversion data storage
• DAC up to 2 channels, R-2R type, 10-bit resolution
• Base timer up to 8 channels, each selectable for 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, or 16/32-bit PWC timer mode
• GPIO ports usable as general-purpose I/O when pins are not assigned to peripherals, with port relocation function, per-pin pull-up control, direct pin level readback, and 5V-tolerant on select ports