ADI AD9272BSVZRL-65

The AD9272 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a low noise preamplifier (LNA) with a variable gain amplifier (VGA), an antialiasing filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-digital converter (ADC). Each channel features a variable gain range of 42 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 80 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input-referred noise voltage is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise voltage of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is about 92 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8×8 differential crosspoint switch. The switch is programmable through the SPI. The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided. Powering down individual channels is supported to increase battery life for portable applications. There is also a standby mode option that allows quick power-up for power cycling. In CW Doppler operation, the VGA, antialiasing filter (AAF), and ADC are powered down. The power of the time gain control (TGC) path scales with selectable speed grades. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the serial port interface. Fabricated in an advanced CMOS process, the AD9272 is available in a 16 mm×16 mm, RoHS-compliant, 100-lead TQFP. It is specified over the industrial temperature range of -40 °C to +85 °C.

• 8 channels of LNA, VGA, AAF, and ADC
• Low noise preamplifier (LNA) Input-referred noise voltage = 0.75 nV/√Hz (gain = 27.3 dB) @5 MHz typical
• SPI-programmable gain = 75.6 dB/17.9 dB/21.3 dB
• Single-ended input; yIN maximum = 733 mV p-p/550 mV p-p/367 mV p-p
• Dual-mode active input impedance matching
• Bandwidth (BW) > 100 MHz
• Full-scale (FS) output = ±4.4 V p-p differential
• Variable gain amplifier (VGA) Attenuator range = -42 dB to 0 dB
• SPI-programmable PGA gain = 27 dB/24 dB/27 dB/30 dB
• Linear-in-dB gain control
• Antialiasing filter (AAF) Programmable 2nd-order low-pass filter (LPF) from 8 MHz to 18 MHz
• Programmable high-pass filter (HPF)
• Analog-to-digital converter (ADC) 12 bits at 10 MSPS to 80 MSPS
• SNR = 70 dB
• SFDR = 75 dB
• Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs
• Includes an 8×8 differential crosspoint switch to support continuous wave (CW) Doppler
• Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)
• 120 mW per channel in CW Doppler
• Flexible power-down modes
• Overload recovery in < 10 ns
• Fast recovery from low power standby mode, < 2 μs
• 100-lead TQFP

• Medical imaging/ultrasound
• Automotive radar