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Alliance Memory AS7C31026B-20TINTR

Producent
Nr części prod.
AS7C31026B-20TINTR
Nr LCSC
C6465861
Opak.
TSOP-442
Numer Klienta
Klucz. cechy
1Mbit Parallel Port (Parallel) TSOP-442 Memory RoHS
Karta KatalogowaAlliance Memory AS7C31026B-20TINTR
Części alternatywne5
Gwarancja na każde zamówienie
100% Oryginalne · Zwrot lub Wymiana w ciągu 30 Dni
Brak w magazynie
Powiadom mnie
Minimum: 1Wielokrotność: 1Jednostka sprzedaży: Piece
Dodaj do Listy BOM
Szt.Cena jedn.(Tylko do wglądu)Suma całkowita
1+$ 8.2429$ 8.24
200+$ 3.2902$ 658.04
500+$ 3.1796$ 1589.80
1,000+$ 3.125$ 3125.00
Standardowa Obudowa1000/Full Reel
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Specyfikacje Produktu

Wszystko
TypOpis
KategoriaIntegrated Circuits (ICs)/Memory/Memory
ProducentAlliance Memory
Opak.TSOP-442
Operating Temperature-40℃~+85℃
FeaturesAuto power-down function
Memory Size1Mbit
Voltage - Supply3V~3.6V;65mA
Access Time20ns
Standby Supply Current5mA
InterfaceParallel Port (Parallel)

Opis

Tłumaczenie AI

The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words x 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of (WE) (write cycle 1) or (CE) (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and (UB) controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry standard packages.

Funkcje

Tłumaczenie AI
  • Industrial and Commercial versions
  • Organization: 65,536 words x 16 bits
  • Center power and ground pins for low noise
  • High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time
  • Low power consumption: ACTIVE - 288 mW / max @ 10 ns
  • Low power consumption: STANDBY - 18 mW / max CMOS I/O
  • Easy memory expansion with CE, OE inputs
  • TTL-compatible, three-state I/O
  • JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin TSOP 2
  • ESD protection ≥2000 volts
  • Latch-up current ≥200 mA

Części alternatywne

MPNProducentTyp alternatywnyOpakowanieDostępnośćCena jednostkowa
AS7C31026B-20TINAlliance MemoryPodobneTSOP-4420$ 8.0417
AS7C31026B-15TINAlliance MemoryPodobneTSOP-4420$ 7.0356
AS7C31026B-15TINTRAlliance MemoryPodobneTSOP-4420$ 7.2376
AS7C31026B-12TINTRAlliance MemoryPodobneTSOP-4420$ 7.2371
AS7C31026B-12TINAlliance MemoryPodobneTSOP-4420$ 7.7104