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EDA-ModelleEasyEDA
MICROCHIP dsPIC33CK256MP205T-I/PT
| Hersteller | |
| Herst.-Teilenr. | dsPIC33CK256MP205T-I/PT |
| LCSC-Nr. | C629237 |
| Verp. | TQFP-48(7x7) |
| Kundennummer | |
| Hauptmerkm. | 100MHz TQFP-48(7x7) Microcontrollers RoHS |
| Datenblatt | MICROCHIP dsPIC33CK256MP205T-I/PT |
| RoHS-Konformität | 2 Dokumente verfügbar |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Hersteller | MICROCHIP | |
| Verp. | TQFP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 100MHz |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Hersteller | MICROCHIP | |
| Verp. | TQFP-48(7x7) |
| Typ | Beschreibung | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 100MHz |
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Merkmale
KI-Übersetzung
- 32 - 256 Kbytes of Program Flash with ECC and 8 - 24K RAM
- Fast 6 - Cycle Divide
- LiveUpdate
- Code Efficient (C and Assembly) Architecture
- 40 - Bit Wide Accumulators
- Single - Cycle (MAC/MPY) with Dual Data Fetch
- Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
- 32 - Bit Multiply Support
- Four Sets of Interrupt Context Saving Registers which include Accumulator and STATUS for Fast Interrupt Handling
- Zero Overhead Looping
- RAM Memory Built - In Self - Test (MBIST)
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Reference Clock Output
- Fail - Safe Clock Monitor (FSCM)
- Fast Wake - up and Start - up
- Backup Internal Oscillator
- Low - Power Management Modes (Sleep, Idle, Doze)
- Integrated Power - on Reset and Brown - out Reset
- Eight PWM Pairs
- Up to 250 ps PWM Resolution
- Dead Time for Rising and Falling Edges
- Dead - Time Compensation
- Clock Chopping for High - Frequency Operation
- Fault and Current Limit Inputs
- Flexible Trigger Configuration for ADC Triggering
- One General Purpose Timer
- Peripheral Trigger Generator (PTG): Up to 15 trigger sources to other peripheral modules
- CPU independent state machine - based instruction sequencer
- Nine MCCP/SCCP modules which Include Timer, Capture/Compare and PWM:
- One MCCP
- Eight SCCPs
- 16 or 32 - bit time base
- 16 or 32 - bit capture
- 4 - deep capture buffer
- Fully Asynchronous Operation, Available in Sleep Modes
- High - Speed ADC module:
- 12 - bit with two dedicated SAR ADC cores and one shared SAR ADC core
- Configurable resolution (up to 12 - bit) for each ADC core
- Up to 3.5 Msps conversion rate per channel at 12 - bit resolution
- Up to 24 input channels
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Four digital comparators
- Four oversampling filters for increased resolution
- Up to Three Analog Comparators: 15 ns analog comparator
- Up to Three Op Amps
- Three 12 - Bit DACs: Hardware slope compensation
- Three Protocol UARTs with Automated Protocol Handling Support for: LIN2.2 DMX IrDA
- Four - Wire SPI/I²S modules
- CAN Flexible Data (FD) module
- Three I²C modules with SMBus Support
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC)
- Two SENT modules
- Parallel Master Port (PMP)
- Four DMA Channels
- In - Circuit and In - Application Programming and Debugging
- Three Complex, Five Simple Breakpoints
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run - Time Watch
- Clock Monitor System with Backup Oscillator
- DMT (Deadman Timer)
- ECC (Error Correcting Code)
- WDT (Watchdog Timer)
- CodeGuard Security
- CRC (Cyclic Redundancy Check)
- Flash OTP by ICSP Write Inhibit
- RAM Memory Built - In Self - Test (MBIST)
- Two - Speed Start - up
- Fail - Safe Clock Monitoring (FSCM)
- Backup FRC (BFRC)
- Capless Internal Voltage Regulator
- Virtual Pins for Redundancy and Monitoring
- Class B Safety Library - IEC 60730
- For ASIL B and Beyond Applications - ISO 26262
- FMEDA Computation Spreadsheet (Evaluation of Random Hardware Failures Metric)
- Functional Safety Manual
- Functional Safety Diagnostics Suite
- AEC - Q100 REV - H (Grade 1: - 40°C to + 125°C) Compliant
- AEC - Q100 REV - H (Grade 0: - 40°C to + 150°C) Compliant
Anwendungen
KI-Übersetzung
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
Garantie auf jede Bestellung
100% Authentisch · 30-Tage-Rückgabe oder -Umtausch
Vorrätig: 50
50 Ab Lager, sofort versandfertig
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
| Stk. | E-Preis | Gesamtbetrag |
|---|---|---|
| 1+ | $ 5.6421 | $ 5.64 |
| 10+ | $ 4.8688 | $ 48.69 |
| 30+ | $ 4.3982 | $ 131.95 |
| 100+ | $ 4.0017 | $ 400.17 |
Standardgehäuse1600/Full Reel | ||
Besserer Preis bei größerer Menge?
$
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Hersteller | MICROCHIP | |
| Verp. | TQFP-48(7x7) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 100MHz |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Hersteller | MICROCHIP | |
| Verp. | TQFP-48(7x7) |
| Typ | Beschreibung | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Clock Rate | 100MHz |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- 32 - 256 Kbytes of Program Flash with ECC and 8 - 24K RAM
- Fast 6 - Cycle Divide
- LiveUpdate
- Code Efficient (C and Assembly) Architecture
- 40 - Bit Wide Accumulators
- Single - Cycle (MAC/MPY) with Dual Data Fetch
- Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
- 32 - Bit Multiply Support
- Four Sets of Interrupt Context Saving Registers which include Accumulator and STATUS for Fast Interrupt Handling
- Zero Overhead Looping
- RAM Memory Built - In Self - Test (MBIST)
- Internal Oscillator
- Programmable PLLs and Oscillator Clock Sources
- Reference Clock Output
- Fail - Safe Clock Monitor (FSCM)
- Fast Wake - up and Start - up
- Backup Internal Oscillator
- Low - Power Management Modes (Sleep, Idle, Doze)
- Integrated Power - on Reset and Brown - out Reset
- Eight PWM Pairs
- Up to 250 ps PWM Resolution
- Dead Time for Rising and Falling Edges
- Dead - Time Compensation
- Clock Chopping for High - Frequency Operation
- Fault and Current Limit Inputs
- Flexible Trigger Configuration for ADC Triggering
- One General Purpose Timer
- Peripheral Trigger Generator (PTG): Up to 15 trigger sources to other peripheral modules
- CPU independent state machine - based instruction sequencer
- Nine MCCP/SCCP modules which Include Timer, Capture/Compare and PWM:
- One MCCP
- Eight SCCPs
- 16 or 32 - bit time base
- 16 or 32 - bit capture
- 4 - deep capture buffer
- Fully Asynchronous Operation, Available in Sleep Modes
- High - Speed ADC module:
- 12 - bit with two dedicated SAR ADC cores and one shared SAR ADC core
- Configurable resolution (up to 12 - bit) for each ADC core
- Up to 3.5 Msps conversion rate per channel at 12 - bit resolution
- Up to 24 input channels
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Four digital comparators
- Four oversampling filters for increased resolution
- Up to Three Analog Comparators: 15 ns analog comparator
- Up to Three Op Amps
- Three 12 - Bit DACs: Hardware slope compensation
- Three Protocol UARTs with Automated Protocol Handling Support for: LIN2.2 DMX IrDA
- Four - Wire SPI/I²S modules
- CAN Flexible Data (FD) module
- Three I²C modules with SMBus Support
- PPS to Allow Function Remap
- Programmable Cyclic Redundancy Check (CRC)
- Two SENT modules
- Parallel Master Port (PMP)
- Four DMA Channels
- In - Circuit and In - Application Programming and Debugging
- Three Complex, Five Simple Breakpoints
- IEEE 1149.2 Compatible (JTAG) Boundary Scan
- Trace Buffer and Run - Time Watch
- Clock Monitor System with Backup Oscillator
- DMT (Deadman Timer)
- ECC (Error Correcting Code)
- WDT (Watchdog Timer)
- CodeGuard Security
- CRC (Cyclic Redundancy Check)
- Flash OTP by ICSP Write Inhibit
- RAM Memory Built - In Self - Test (MBIST)
- Two - Speed Start - up
- Fail - Safe Clock Monitoring (FSCM)
- Backup FRC (BFRC)
- Capless Internal Voltage Regulator
- Virtual Pins for Redundancy and Monitoring
- Class B Safety Library - IEC 60730
- For ASIL B and Beyond Applications - ISO 26262
- FMEDA Computation Spreadsheet (Evaluation of Random Hardware Failures Metric)
- Functional Safety Manual
- Functional Safety Diagnostics Suite
- AEC - Q100 REV - H (Grade 1: - 40°C to + 125°C) Compliant
- AEC - Q100 REV - H (Grade 0: - 40°C to + 150°C) Compliant
Anwendungen
KI-Übersetzung
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
C629237 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Typ | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |