Infineon CY9BF129TAPMC-GK7CGE2

The MB9B120TA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C, LIN).

• 32-bit Arm Cortex-M3 Core
  • Processor version: r2p1
  • Up to 60 MHz Frequency Operation
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
  • 24-bit System timer (Sys Tick): System timer for OS task management
• On-chip Memories
  • [Flash memory]
    • Dual operation Flash memory
      • Main area: Up to 1.5 Mbytes (1008 Kbytes(ROM0) + 512 Kbytes (ROM1) of Upper bank and 16 Kbytes (ROM0) of Lower bank.)
      • Work area: 64 Kbytes(ROM1) of Lower bank
    • Read cycle: 0 wait-cycle
    • Security function for code protection
  • [SRAM]
    • This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
    • SRAM0: Up to 96 Kbytes
    • SRAM1: Up to 96 Kbytes
• External Bus Interface
  • Supports SRAM, NOR NAND Flash memory device
  • Up to 8 chip selects
  • 8-/16-bit Data width
  • Up to 25-bit Address bit
  • Maximum area size: Up to 256 Mbytes
  • Supports Address/Data multiplex
  • Supports external RDY function
• Multi-function Serial Interface (Max 16channels)
  • 16 channels with 16 steps ×9-bit FIFO
  • Operation mode is selectable from the followings for each channel: UART, CSIO, LIN, I2C
  • [UART]
    • Full duplex double buffer
    • Selection with or without parity supported
    • Built-in dedicated baud rate generator
    • External clock available as a serial clock
    • Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
    • Various error detection functions available (parity errors, framing errors, and overrun errors)
  • [CSIO]
    • Full duplex double buffer
    • Built-in dedicated baud rate generator
    • Overrun error detection function available
  • [LIN]
    • LIN protocol Rev.2.1 supported
    • Full duplex double buffer
    • Master/Slave mode supported
    • LIN break field generation (can be changed to 13 to 16-bit length)
    • LIN break delimiter generation (can be changed to 1 to 4-bit length)
    • Various error detection functions available (parity errors, framing errors, and overrun errors)
  • [I2C]
    • Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps) supported
• DMA Controller (8channels)
  • The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the built-in peripherals
  • Transfer address area: 32-bit (4 Gbytes)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: byte/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
• A/D Converter (Max 24channels)
  • [12-bit A/D Converter]
    • Successive Approximation type
    • Built-in 2units
    • Conversion time: 1.0μs @ 2.7V to 5.5V
    • Priority conversion available (priority at 2 levels)
    • Scanning conversion mode
    • Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
• D/A Converter (Max 2 channels)
  • R-2R type 10-bit resolution
• Base Timer (Max 16channels)
  • Operation mode is selectable from the followings for each channel: 16-bit PWM timer, 16-bit PPG timer, 16-/32-bit reload timer, 16-/32-bit PWC timer
• General-Purpose I/O Port
  • This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
  • Capable of pull-up control per pin
  • Capable of reading pin level directly
  • Built-in the port relocate function
  • Up to 154 high-speed general-purpose I/O Ports@176 pin Package
  • Some ports are 5V tolerant.
• Dual Timer (32-/16-bit Down Counter)
  • The Dual Timer consists of two programmable 32-/16-bit down counters.
  • Operation mode is selectable from the followings for each channel: Free-running, Periodic (= Reload), One-shot
• Quadrature Position/Revolution Counter (QPRC) (Max 2channels)
  • The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.
  • The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
  • 16-bit position counter
  • 16-bit revolution counter
  • Two 16-bit compare registers
• HDMI-CEC/Remote Control Reception (Up to 2channels)
  • HDMI-CEC transmission
    • Header block automatic transmission by judging Signal free
    • Generating status interrupt by detecting Arbitration lost
    • Generating START, EOM, ACK automatically to output CEC transmission by setting 1