TI 5962-89687013A

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry for multiplexing data directly from the data bus or from internal storage registers. Output enable (OEAB and OEBA) inputs are provided to control the transceiver function. Select control (SAB and SBA) inputs are provided to select real-time or stored-data transfer. The circuitry used for select control eliminates the typical decoding glitches that occur in multiplexers during switching between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data. Data on the A bus or B bus, or both, can be stored in the internal D-type flip-flops on the low-to-high transition of the respective clock (CLKAB or CLKBA), and this storage operation is independent of the state of the select control or output control inputs. When SAB and SBA are in the real-time transfer mode, data storage in the internal D-type flip-flops can be bypassed by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input signal. When all other data sources on both buses are in the high-impedance state, each bus will retain its last state. The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the recommended maximum IOL is increased to 48 mA for the -1 versions. No -1 versions are available for the SN54ALS652, SN54ALS653, SN74ALS653, or SN74ALS654.

• Bus transceivers/registers
• Independent registers and enables for A-bus and B-bus
• Multiplexable real-time and stored data
• Selectable non-inverting or inverting data path
• Selectable 3-state or open-collector output to A-bus