TI DS90UB913QSQX/NOPB

The DS90UB91xQ-Q1 chipset provides an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. Both the high-speed forward channel and the bidirectional control channel data paths of the DS90UB91xQ-Q1 chipset include differential signaling. The serializer/deserializer pair is mainly used to connect the imager and the video processor in the electronic control unit (ECU). This chipset is well-suited for driving video data that requires up to 12-bit pixel depth, 2 synchronization signals, and a bidirectional control channel bus. With embedded clock technology, transparent full-duplex communication can be achieved over a single differential pair, carrying asymmetric bidirectional control channel information in both directions. This single serial data stream simplifies the transmission of wide data buses on printed circuit board (PCB) traces and cables by eliminating the skew between parallel data and clock paths. In this way, by limiting the path width, the system cost is greatly reduced, and correspondingly, the number of PCB layers, cable width, and the size and pin count of connectors are reduced. In addition, the deserializer input also provides an adaptive equalization function to compensate for losses on long-distance media. Internal DC equalization encoding and decoding are used to support AC-coupled interconnections.

• 10MHz to 100MHz input pixel clock support
• Single differential pair interconnect
• Programmable data payload:
  • 10-bit payload, up to 100MHz
  • 12-bit payload, up to 75MHz
• Continuous low-latency bidirectional control interface channel, I²C support up to 400kHz
• 2:1 multiplexer for selection between two input imagers
• Embedded clock with DC-balanced encoding, AC-coupled interconnect support
• Capable of driving shielded twisted pair up to 25 meters
• Receive equalizer auto-adapts to cable loss variations
• 4 dedicated GPIO pins available on both serializer and deserializer
• LOCK output reporting pin and AT-SPEED BIST diagnostic feature for link integrity verification

• Front or rear camera for surround view in collision mitigation and parking assist systems