micron MT58V512V36DT-7.5

This synchronous burst SRAM family is designed with high-speed, low-power CMOS technology and fabricated using an advanced CMOS process. These 18-Mbit synchronous burst SRAMs integrate a 1M×18, 512K×32, or 512K×36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs are controlled by registers clocked by a single positive edge-triggered clock input. Synchronous inputs include all addresses, all data inputs, active-low chip enable, two additional chip enables for simplified depth expansion, burst control inputs, byte write enables, and a global write enable. Asynchronous inputs include output enable, clock enable, and sleep mode enable. A burst mode input is also provided to select either interleaved or linear burst mode. Data outputs are controlled by the output enable. Write cycle width can be one to two bytes or one to four bytes, as determined by the write control inputs. Burst operations can be initiated by an address status processor or address status controller input. Subsequent burst addresses are generated internally under control of the burst advance input. Addresses and write controls are registered on-chip to simplify write cycles and achieve self-timed write operation. Individual byte enables allow writing to single bytes. Asserting the global write enable low writes all bytes. Parity bits are available only in specific versions. The device includes an additional pipeline enable register that delays the deactivation of output buffers by one additional cycle when a deselect is executed. This feature allows depth expansion without compromising system performance. The device is ideally suited for pipelined systems requiring wide, high-speed data buses, as well as general-purpose 16-bit, 18-bit, 32-bit, 36-bit, 64-bit, and 72-bit wide applications.

• Fast clock and output enable access times
• Single 3.3V ±5% or 2.5V ±5% supply voltage
• Separate 3.3V ±5% or 2.5V ±5% isolated output buffer supply
• Sleep mode for reduced standby power consumption
• Common data input and output
• Separate byte write control and global write control
• Three chip enables for depth expansion and address pipelining
• Clock-controlled address, data I/O, and control signal registers
• Internal self-timed write cycle
• Burst control
• Low capacitance bus loading
• Multiple timing, configuration, package, and operating temperature range options

• Pentium and PowerPC pipeline systems
• General-purpose 16-bit applications
• General-purpose 18-bit applications
• General-purpose 32-bit applications
• General-purpose 36-bit applications