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ADI AD9609BCPZRL7-80

Hersteller
Herst.-Teilenr.
AD9609BCPZRL7-80
LCSC-Nr.
C653620
Verp.
LFCSP-32(5x5)
Kundennummer
Hauptmerkm.
Parallel port 1.8V~3.3V LFCSP-32(5x5) Analog to Digital Converters (ADC) RoHS
DatenblattADI AD9609BCPZRL7-80
RoHS-Konformität1 Dokumente verfügbar
Alternativteile4
Garantie auf jede Bestellung
100% Authentisch · 30-Tage-Rückgabe oder -Umtausch
Nicht vorrätig
Benachrichtigen
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 9.8304$ 9.83
200+$ 3.8047$ 760.94
500+$ 3.6704$ 1835.20
1,500+$ 3.6056$ 5408.40
Standardgehäuse1500/Full Reel
Besserer Preis bei größerer Menge?
$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
HerstellerADI
Verp.LFCSP-32(5x5)
Operating Temperature-40℃~+85℃
InterfaceParallel port
Quiescent Current (Iq)-
Voltage - Supply1.8V~3.3V
Number of Channels1
Integral non - linearity0.45LSB
Voltage ReferenceBuilt-in
Clock/OscillatorExternal
Clock Frequency-
FeaturesSoft reset
Resolution(Bits)80MHz;10
S/N Ratio61.5dB
ADC architecturePipeline
Programmable Gain-

Beschreibung

KI-Übersetzung

The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input with selectable internal 1 to 8 divide ratio controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported. The AD9609 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (-40°C to +85°C).

Merkmale

KI-Übersetzung
  • 1.8 V analog supply operation
  • 1.8 V to 3.3 V output supply
  • SNR 61.5 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input
  • SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input
  • Low power 45 mW at 20 MSPS 76 mW at 80 MSPS
  • Differential input with 700 MHz bandwidth
  • On-chip voltage reference and sample-and-hold circuit
  • 2 V p-p differential analog input
  • DNL = ±0.10 LSB
  • Serial port control options
  • Offset binary, gray code, or twos complement data format
  • Optional clock duty cycle stabilizer
  • Integer 1-to-8 input clock divider
  • Built-in selectable digital test pattern generation
  • Energy-saving power-down modes
  • Data clock out with programmable clock and data alignment

Anwendungen

KI-Übersetzung
  • Communications
  • Diversity radio systems
  • Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
  • Smart antenna systems
  • Battery-powered instruments
  • Handheld scope meters
  • Portable medical imaging
  • Ultrasound
  • Radar/LIDAR
  • PET/SPECT imaging

Alternativteile

MPNHerstellerVerpackungVerfügbarkeitStückpreis
AD9609BCPZRL7-65ADILFCSP-32(5x5)0$ 9.105
AD9215BCPZ-80ADILFCSP-32(5x5)0$ 15.7902
AD9215BCPZ-105ADILFCSP-32(5x5)0$ 23.469
AD9215BCPZ-65ADILFCSP-32(5x5)0$ 29.9652