Nexperia 74AUP1G373GN,132
| 제조업체 | |
| 제조사 품번 | 74AUP1G373GN,132 |
| LCSC 번호 | C545850 |
| 포장 | XSON-6(0.9x1) |
| 고객 번호 | |
| 주요 제원 | D Latch 0.8V~3.6V 1 2.5ns XSON-6(0.9x1) Latches RoHS |
| 데이터시트 | Nexperia 74AUP1G373GN,132 |
| RoHS 준수 | 2개 문서 이용 가능 |
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | Nexperia | |
| 포장 | XSON-6(0.9x1) | |
| Quiescent Current | 1.4uA | |
| Series | 74AUP | |
| Logic Type | D Latch | |
| Voltage - Supply | 0.8V~3.6V | |
| Operating Temperature | -40℃~+125℃ | |
| Current - Output Low(IOL) | 4mA | |
| Output Type | Tri-State | |
| Number of Gates | 1 | |
| Setup Time | - | |
| Current - Output High(IOH) | 4mA | |
| Hold Time | - | |
| Propagation Delay | 2.5ns |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | Nexperia | |
| 포장 | XSON-6(0.9x1) | |
| Quiescent Current | 1.4uA | |
| Series | 74AUP | |
| Logic Type | D Latch | |
| Voltage - Supply | 0.8V~3.6V | |
| Operating Temperature | -40℃~+125℃ |
| 타입 | 설명 | |
|---|---|---|
| Current - Output Low(IOL) | 4mA | |
| Output Type | Tri-State | |
| Number of Gates | 1 | |
| Setup Time | - | |
| Current - Output High(IOH) | 4mA | |
| Hold Time | - | |
| Propagation Delay | 2.5ns |
개요
The 74AUP1G373 is a single D-type transparent latch; 3-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
주요 특징
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- CMOS low power dissipation
- Low static power consumption; ICC = 0.9 μA (maximum)
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
응용 분야
- Low-power D-type transparent latch; 3-state
| 수량 | 단가(참고용) | 총액 |
|---|---|---|
| 1+ | $ 0.4818 | $ 0.48 |
| 200+ | $ 0.1874 | $ 37.48 |
| 500+ | $ 0.1811 | $ 90.55 |
| 1,000+ | $ 0.178 | $ 178.00 |
표준 패키지5000/Full Reel | ||
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | Nexperia | |
| 포장 | XSON-6(0.9x1) | |
| Quiescent Current | 1.4uA | |
| Series | 74AUP | |
| Logic Type | D Latch | |
| Voltage - Supply | 0.8V~3.6V | |
| Operating Temperature | -40℃~+125℃ | |
| Current - Output Low(IOL) | 4mA | |
| Output Type | Tri-State | |
| Number of Gates | 1 | |
| Setup Time | - | |
| Current - Output High(IOH) | 4mA | |
| Hold Time | - | |
| Propagation Delay | 2.5ns |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Logic/Latches | |
| 제조업체 | Nexperia | |
| 포장 | XSON-6(0.9x1) | |
| Quiescent Current | 1.4uA | |
| Series | 74AUP | |
| Logic Type | D Latch | |
| Voltage - Supply | 0.8V~3.6V | |
| Operating Temperature | -40℃~+125℃ |
| 타입 | 설명 | |
|---|---|---|
| Current - Output Low(IOL) | 4mA | |
| Output Type | Tri-State | |
| Number of Gates | 1 | |
| Setup Time | - | |
| Current - Output High(IOH) | 4mA | |
| Hold Time | - | |
| Propagation Delay | 2.5ns |
개요
The 74AUP1G373 is a single D-type transparent latch; 3-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
주요 특징
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- CMOS low power dissipation
- Low static power consumption; ICC = 0.9 μA (maximum)
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
응용 분야
- Low-power D-type transparent latch; 3-state
C545850 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| 타입 | 세부사항 |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |