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ADI AD7864ASZ-1REEL

Fabricante
Cód. da peça
AD7864ASZ-1REEL
Nº LCSC
C514250
Emb.
MQFP-44(10x10)
Número do Cliente
Atrib. princ.
4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC
Folha de DadosADI AD7864ASZ-1REEL
Conformidade RoHS1 documentos disponíveis
Peças alternativas5
Garantia em cada pedido
100% Autêntico · Devolução ou Substituição em 30 Dias

Especificações do Produto

Tudo
TipoDescrição
CategoriaIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
FabricanteADI
Emb.MQFP-44(10x10)
Operating Temperature-40℃~+85℃
InterfaceParallel Port
Quiescent Current (Iq)20uA
Voltage - Supply5V
Number of Channels4
Integral non - linearity1LSB
Voltage ReferenceBuilt-in
Clock/OscillatorBuilt-in
Clock Frequency5MHz
FeaturesBipolar input;Multi-chip synchronization;Simultaneous sampling;Synchronous triggering
Resolution(Bits)500kHz;12
S/N Ratio70dB
DNL (LSB)0.9LSB
ADC architectureSAR
Programmable GainNot supported

Descrição

Tradução por IA

The AD7864 is a high speed, low power, 4-channel, simultaneous sampling 12-bit analog-to-digital converter (ADC) that operates from a single 5 V supply. The part contains a 1.65 μs successive approximation ADC, four track-and-hold amplifiers, a 2.5 V reference, an on-chip clock oscillator, signal conditioning circuitry, and a high speed parallel interface. The input signals on four channels sample simultaneously preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ±10 V, ±5 V (AD7864-1), 0 V to +2.5 V, 0 V to +5 V (AD7864-2), and ±2.5 V (AD7864-3). Any subset of the four channels can be converted to maximize the throughput rate on the selected sequence. Select the channels to convert via hardware (channel select input pins) or software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track-and-holds into hold and initiates a conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. Data is read from the part by a 12-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 500 kSPS. For all four channels, the maximum throughput is 130 kSPS for the read-during-conversion sequence operation. The throughput rate for the read-after-conversion sequence operation depends on the read cycle time of the processor.

Recursos

Tradução por IA
  • High speed <1.65 μs> 12-bit ADC
  • 4 simultaneously sampled inputs
  • 4 track-and-hold amplifiers 0.35 μs track-and-hold acquisition time 1.65 μs conversion time per channel
  • HW/SW select of channel sequence for conversion
  • Single-supply operation
  • Selection of input ranges ±10 V, ±5 V for AD7864-1 ±2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2
  • High speed parallel interface that allows Interfacing to 3 V processors
  • Low power, 90 mW typical
  • Power saving mode, 20 μW typical
  • Overvoltage protection on analog inputs

Aplicações

Tradução por IA
  • AC motor control
  • Uninterrupted power supplies
  • Data acquisition systems
  • Communications