Rochester Electronics 54F648/BLA

These devices consist of bus transceiver circuits with three-state outputs, D-type flip-flops, and control circuitry for multiplexing data directly from the input bus or internal registers. When the respective clock pin transitions to a logic high level, data on the A or B bus is clocked into the registers. A control pin G̅ and a direction pin are provided to control the transceiver function. In transceiver mode, data on the high-impedance port can be stored in the A register, the B register, or both simultaneously. Select controls allow multiplexing of stored data and real-time (transparent mode) data. When the output-enable control pin G̅ is low, the direction control determines which bus receives the data. In isolation mode (control pin G̅ high), A data can be stored in the B register and B data can be stored in the A register.

• Separate registers for A and B buses
• Multiplexed real-time and stored data
• F648 features inverting data path
• F646/F646B features non-inverting data path
• F646B is a faster version of F646
• Three-state outputs
• 300 mil slim DIP package
• Guaranteed minimum 4000V ESD protection