ADI HMC699LP5E
| 제조업체 | |
| 제조사 품번 | HMC699LP5E |
| LCSC 번호 | C3608148 |
| 포장 | QFN-32(5x5) |
| 고객 번호 | |
| 주요 제원 | 7GHz 4.75V~5.25V 2 QFN-32(5x5) Clock Generators, PLLs, Frequency Synthesizers RoHS |
| 데이터시트 | ADI HMC699LP5E |
| RoHS 준수 | 1개 문서 이용 가능 |
| 대체 부품 | 1 |
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| 제조업체 | ADI | |
| 포장 | QFN-32(5x5) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | External | |
| Output Frequency(Max) | 7GHz | |
| Voltage - Supply | 4.75V~5.25V | |
| Period Jitter, Peak-to-Peak | -;- | |
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| 제조업체 | ADI | |
| 포장 | QFN-32(5x5) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | External | |
| Output Frequency(Max) | 7GHz | |
| Voltage - Supply | 4.75V~5.25V | |
| Period Jitter, Peak-to-Peak | -;- |
| 타입 | 설명 | |
|---|---|---|
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
개요
The HMC699LP5(E) is a frequency synthesizer with a wideband reversible polarity digital PFD and lock detect output. The divider operates from 160 - 7000 MHz with a continuous integer division ratio N = 56 to 519 and non-continuous division ratio N = 16 to 54. The HMC699LP5(E) high frequency operation along with ultra low phase noise floor make possible synthesizers with wide loop bandwidth and low N resulting in fast settling and very low phase noise. When used in conjunction with a differential loop filter, the HMC699LP5(E) can be used to phase lock a VCO to a reference oscillator. For continuous division ratio, the A counter and S counter must satisfy the condition: A + 1 ≥ S.
주요 특징
- Ultra Low SSB Phase Noise Floor: -153 dBc/Hz @ 10 kHz offset @ 100 MHz Reference Frequency.
- Programmable Divider (N = 16 - 519) operating up to 7 GHz
- Open Collector Output Buffer Amplifiers for Interfacing w/ Op-Amp Based Loop Filter
- Reversible Polarity PFD w/ Lock Detect Output
- 32 Lead 5x5mm SMT Package: 25mm²
응용 분야
- Satellite Communication Systems
- Point-to-Point Radios
- Sonet Clock Generation
| 수량 | 단가(참고용) | 총액 |
|---|---|---|
| 1+ | $ 135.976 | $ 135.98 |
| 200+ | $ 52.6215 | $ 10524.30 |
| 500+ | $ 50.772 | $ 25386.00 |
| 1,000+ | $ 49.8588 | $ 49858.80 |
표준 패키지500/Full Reel | ||
제품 사양
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| 제조업체 | ADI | |
| 포장 | QFN-32(5x5) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | External | |
| Output Frequency(Max) | 7GHz | |
| Voltage - Supply | 4.75V~5.25V | |
| Period Jitter, Peak-to-Peak | -;- | |
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
| 타입 | 설명 | |
|---|---|---|
| 카테고리 | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| 제조업체 | ADI | |
| 포장 | QFN-32(5x5) | |
| Operating Temperature | -40℃~+85℃ | |
| Clock/Oscillator | External | |
| Output Frequency(Max) | 7GHz | |
| Voltage - Supply | 4.75V~5.25V | |
| Period Jitter, Peak-to-Peak | -;- |
| 타입 | 설명 | |
|---|---|---|
| Interface | - | |
| Phase Offset | - | |
| Features | - | |
| Input | - | |
| Output Level | - | |
| Phase Jitter | - | |
| Number of Outputs | 2 |
개요
The HMC699LP5(E) is a frequency synthesizer with a wideband reversible polarity digital PFD and lock detect output. The divider operates from 160 - 7000 MHz with a continuous integer division ratio N = 56 to 519 and non-continuous division ratio N = 16 to 54. The HMC699LP5(E) high frequency operation along with ultra low phase noise floor make possible synthesizers with wide loop bandwidth and low N resulting in fast settling and very low phase noise. When used in conjunction with a differential loop filter, the HMC699LP5(E) can be used to phase lock a VCO to a reference oscillator. For continuous division ratio, the A counter and S counter must satisfy the condition: A + 1 ≥ S.
주요 특징
- Ultra Low SSB Phase Noise Floor: -153 dBc/Hz @ 10 kHz offset @ 100 MHz Reference Frequency.
- Programmable Divider (N = 16 - 519) operating up to 7 GHz
- Open Collector Output Buffer Amplifiers for Interfacing w/ Op-Amp Based Loop Filter
- Reversible Polarity PFD w/ Lock Detect Output
- 32 Lead 5x5mm SMT Package: 25mm²
응용 분야
- Satellite Communication Systems
- Point-to-Point Radios
- Sonet Clock Generation
C3608148 EasyEDA 라이브러리
컴플라이언스 & 수출 코드
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| 타입 | 세부사항 |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| 타입 | 세부사항 |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

